Browse Prior Art Database

Apparatus for Attaining a Scalable Search Range

IP.com Disclosure Number: IPCOM000118440D
Original Publication Date: 1997-Feb-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 92K

Publishing Venue

IBM

Related People

Boice, CE: AUTHOR [+3]

Abstract

Multiple S-Chip Configurations.

This text was extracted from an ASCII text file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Apparatus for Attaining a Scalable

Search

Range

Multiple S-Chip Configurations:

      An S-chip can support a maximum search window of 80 H,
56V.  To achieve larger search window support, multiple S-chips
can be used.  By using a two S-chip configuration to extend the
horizontal dimension, the search window can be increased to a maximum
of  160 H.  By using a two S-chip configuration to extend the
vertical dimension, the search window can be increased to a maximum
of  112 V.  By using a four S-chip configuration, both the
horizontal and vertical dimensions of the search window can be
increased to support a  maximum search window of  160 H,  112V.
See Table.

      Each S-chip in a multi S-chip configuration is assigned a chip
id.  The three bit chip ids are initialized by hardwiring the
corresponding three inputs on each chip to the card which the S-chips
populate.  The inputs are hardwired to the appropriate voltage levels
to produce the binary ids of 001, 010, 011, or 100.  The S-chips are
configured in a chain in order of increasing ids.  The I-chip only
communicates with the first S-chip in the chain (S-chip 1).  All
initialization commands and pixel data from the I-chip are sent to
the S-chips in a serial fashion, with each S-chip passing the data to
the next S-chip in succession through data buses specific to this
purpose.  In addition to the S-chip, the I-chip must also drive this
data to the R-chip.  Therefore, in order to minimize loading on the
output buses of the I-chip, this serial design was implemented.
Initialization commands from the R-chip, however, are sent to the
S-chips in parallel.  Final search results from the cooperative
S-chip searches are  sent back the chain and are communicated to the
R-chip for refinement by  the first S-chip in the chain.  Chip ids in
a two chip configuration must  be 1 and 2.  Likewise, chip ids in a
four chip...