Browse Prior Art Database

Efficient Release of Storage when Exiting a Thread

IP.com Disclosure Number: IPCOM000118476D
Original Publication Date: 1997-Feb-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Chao, T: AUTHOR [+4]

Abstract

Disclosed is an efficient method for release of computer memory (storage) when a program exits a thread (task or process).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 65% of the total text.

Efficient Release of Storage when Exiting a Thread

      Disclosed is an efficient method for release of computer memory
(storage) when a program exits a thread (task or process).

      On systems using virtual address translation and Translation
Buffers (TLBs), there is a problem reusing the real storage pages and
the virtual storage address without invalidating the address in the
TLB.  In System/370* architecture, there are two ways to invalidate
the address.  The first is to use the IPTE instruction, which will
invalidate one page of memory (4K) at a time.  The other is to do a
PTLB, which purges all addresses from the TLB.  The problem with
using the IPTE instruction is that it is fairly expensive (in terms
of CPU cycles) and to use it for large amounts of storage (1M)
becomes unmanageable.  The problem with PTLB is the frequency that it
is needed.  In a high volume transaction system, threads will be
created and exited at a very high rate.  If PTLBs are performed more
than 1 per second, the value of the TLB is lost.

      This disclosure describes a method for efficient release of
storage when exiting a thread.  When a thread exits, the pages used
as the thread's part of the shared address space are added to a
pending list along with a time stamp.  The time that each CPU issues
a PTLB is  also saved.  Whenever pages are to be added to the pending
list, the time stamps are checked against all CPU PTLB times.  If
PTLBs have been  done on all CP...