Browse Prior Art Database

Low Power Rail-to-Rail Complementary Metal Oxide Semiconductor Operational Amplifier

IP.com Disclosure Number: IPCOM000118497D
Original Publication Date: 1997-Mar-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Nishikawa, H: AUTHOR

Abstract

Disclosed is a circuit to reduce power consumption of Complementary Metal Oxide Semiconductor (CMOS) rail-to-rail operational amplifier. Field Effect Transistor (FET) diodes are placed to reduce the current through P-Channel Field Effect Transistor (PFET) to N-Channel Field Effect Transistor (NFET) of push-pull output stage by forcing the gate voltage.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 93% of the total text.

Low Power Rail-to-Rail Complementary Metal Oxide Semiconductor Operational
Amplifier

      Disclosed is a circuit to reduce power consumption of
Complementary Metal Oxide Semiconductor (CMOS) rail-to-rail
operational amplifier.  Field Effect Transistor (FET) diodes are
placed to reduce the current through P-Channel Field Effect
Transistor (PFET) to N-Channel  Field Effect Transistor (NFET) of
push-pull output stage by forcing the gate voltage.

      The Figure shows a common rail-to-rail operational
amplifier.  This circuit has two source-coupled pairs to drive
push-pull output stage.  The output voltage is determined by the
balance of gate  voltage of T5 and T6, and the gate voltage is
determined by the balance of the input and load of the source-coupled
pair, T1 and T2, T3 and T4, respectively.  The gate voltage can be
any value, if they are in balance, and unable to control because both
sides are drain. If the gate voltage is large in balance, large
current flows through T5 to T6, and this current is of no use because
it does not drive the output load.  Then two FET diodes, designated
as T7 and T8, are placed to lower the gate voltage.  The gate voltage
changes within the range of the diode voltage.  Therefore, the gate
voltage will not be too large and the current through T5 to T6 can be
reduced.  This circuit is Power Supply Voltage (VDD) independent
because both T5 and T7 are connected to a VDD.

      This method can reduce the power dissipatio...