Browse Prior Art Database

Silicon C4 Mask

IP.com Disclosure Number: IPCOM000118498D
Original Publication Date: 1997-Mar-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 82K

Publishing Venue

IBM

Related People

Palagonia, AM: AUTHOR

Abstract

Disclosed is a silicon evaporation mask for forming Pb/Sn bumps on semiconductor devices. Because the mask is fabricated from the same material as the wafer thermal, mismatch is not a problem.

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This is the abbreviated version, containing approximately 61% of the total text.

Silicon C4 Mask

      Disclosed is a silicon evaporation mask for forming Pb/Sn bumps
on semiconductor devices.  Because the mask is fabricated from the
same material as the wafer thermal, mismatch is not a problem.

      In a first embodiment, the mask is fabricated from <100>
silicon wafers that have been thinned by Chemical Mechanical
Polishing (CMP).  By using a very strong basic etchant, the silicon
will etch preferentially along the <111> plane.  By etching from both
sides, a "V" edge will be produced (Fig. 1).  Fig. 2 describes the
critical dimensions.  "m" is the opening in the center of the hole,
"s" is the minimum flat at the top and bottom of the surface of the
mask and "p" is center to center pitch of the holes.  If these are
fixed, then simple geometry gives values for "t" the hole size at the
top and bottom of the hole and "d" the thickness of the silicon.
Fig. 3 shows a basic process sequence of a) After thinning wafer to
thickness "d" form an oxide on top and bottom of the wafer, b) define
openings in the oxide on both sides, c) etch the silicon
preferentially (an example etchant would be concentrated Tetramethyl
ammonium hydroxide), d) strip oxide.

      In a second embodiment of the invention, a rib structure is
formed in the mask to increase mechanical strength (Fig. 4).  The rib
would be formed to align over the  wafer streets.  In this embodiment
the holes are etched only from one side, opposite from the rib side
of the mask (Fig....