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Asynchronous Architectures for Transposition Matrix Circuits

IP.com Disclosure Number: IPCOM000118499D
Original Publication Date: 1997-Mar-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 168K

Publishing Venue

IBM

Related People

Kudva, P: AUTHOR [+2]

Abstract

Disclosed are two asynchronous architectures for performing matrix transposition using a two-dimensional pipeline. These architectures (one based on two-phase signaling, one based on four-phase signaling) have better characteristics than the clocked solution in terms of latency and power, at no cost in area or throughput.

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Asynchronous Architectures for Transposition Matrix Circuits

      Disclosed are two asynchronous architectures for performing
matrix transposition using a two-dimensional pipeline.  These
architectures (one based on two-phase signaling, one based on
four-phase signaling) have better characteristics than the clocked
solution in terms of latency and power, at no cost in area or
throughput.

      Synchronous pipelines are used widely in Digital Signal
Processing (DSP) applications, mainly because of their relative
simplicity and the familiarity that digital logic designers have with
them.  However, in many applications, synchronous pipelines are not
the best solution:  because of the rigidity of the synchronous
scheme, this type of pipeline cannot take advantage of variations in
the data rate.  Also, it is sometimes hard to translate knowledge of
idle stages in the pipeline into power savings.  Asynchronous
pipelines (1) can be used successfully to solve DSP problems (2).  It
is not always  possible to have a completely asynchronous solution
for DSP applications,  due to the clocked nature of real-time input
and output data.  The best  of both worlds is obtained by mixing
synchronous and asynchronous stages,  but the interface between
synchronous and asynchronous has to be introduced in the right place.

      Parts of the pipeline used in block-based image compression and
decompression have been targeted.  This pipeline is very deep, with
successive stages performing very different functions at very
different rates.  One of the stages of the pipeline performs matrix
transposition.  Matrix transposition appears in the computation of
two-dimensional transforms such as the Discrete Cosine Transform
(DCT) (3) and Inverse DCT (IDCT).  It is sometimes possible to
decompose a two-dimensional transform into two one-dimensional
transforms, as is the case for the DCT/IDCT: the one-dimensional DCT
is first applied by  rows and then applied by columns.  A
transposition operation is necessary  between the two one-dimensional
DCTs.

Two-dimensional pipeline

      Two-phase pipelines have a simple control and datapath, high
throughput (data is transferred on both transitions of the control
signal) and will absorb part of the difference in speed between the
reader and writer of the pipeline.  The aim is to design an
asynchronous architecture that has a similar structure to that shown
in Fig. 1.  This architecture will be modified to take advantage of
the elastic properties of the asynchronous pipeline.  Also, at the
moment of switching the matrix from row to column shifting, all
stages of the pipeline have to be synchronized.  Synchronization is
automatic in the clocked architecture but has to be computed for the
asynchronous architecture.

      The matrix is alternatively filled up by rows and by columns
and emptied by columns and by rows.  The matrix is thus in two
different modes of operation, column-mode and r...