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Method to Analyze Worst-Case Simultaneous Switching Delay

IP.com Disclosure Number: IPCOM000118507D
Original Publication Date: 1997-Mar-01
Included in the Prior Art Database: 2005-Apr-01

Publishing Venue

IBM

Related People

Burks, TM: AUTHOR [+3]

Abstract

Disclosed is a method to generate the worst-case simultaneous switching delay rules, which requires the simulation of at most 2n-1 input patterns for a gate with n inputs. Also, an analytical formula is proposed, which can model more accurately the dependence on the arrival time differences. With the addition of these small number of rule equations, a static timer can be extended to include simultaneous switching delays in the timing analysis of Very Large Scale Integration (VLSI) circuits.

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Method to Analyze Worst-Case Simultaneous Switching Delay

    Disclosed is a method to generate the worst-case simultaneous
switching delay rules, which requires the simulation of at most 2n-1
input patterns for a gate with n inputs.  Also, an analytical formula
is proposed, which can model more accurately the dependence on the
arrival time differences.  With the addition of these small number of
rule equations, a static timer can be extended to include
simultaneous switching delays in the timing analysis of Very Large
Scale Integration  (VLSI) circuits.

    The static timing analysis consists of two phases:  the
characterization phase in which rules are generated for all gates of
a book library and the timing analysis phase in which a static timer
incorporating these rules is used to analyze circuits made of gates.
During the characterization phase, a large sample of circuit
simulation runs is applied to each logic gate, which produces a set
of delay and slew rules.  These rules specify the worst-case and
best-case delay and output slew from one input pin to the output pin
as a function of input slew (transition time) T sub x  and output
capacitance loading C sub l:
                                                       eqno (1)
  delay %%'or'%% output %% slew = (K sub 1 + K sub 2  C sub l)
   T sub x + K sub 3  C sub l sup 2 + K sub 4 C sub l + K sub 5

During the late-mode analysis phase, the worst-case rules are
deployed in a static timer such as STEP and EinsTimer to propagate
the signals and slacks through the circuits.

    Rules in Equation (1) are usually obtained under the assumption
that only the input pin under consideration is switching.  Since the
single switching delay does not represent the worst case situation,
the late mode arrival time calculated may be under-estimated.  As a
result, the worst case delay along the critical paths, which is used
for the determination of clock period, may be under-estimated.  This
may impact the correct verification of machine operation.  Consider a
simple CMOS two-input NAND gate, which consists of two n-transistors
in series and two p-transistors in parallel.  When two inputs switch
from 0 to 1 at the same time, two n-transistors in series switch on
simultaneously and give rise to a delay, which is worse than the
switching delay of any single input lbracket 1 rbracket .

For a gate with n inputs, two complex problems occurs:
  1.  During the characterization phase, a complete set of
       delay rules requires 4 sup n  simulation runs, each
       corresponding to a combination of input patterns, with
       input signals taking value of 0, 1, r(ising) and f(alling).
  2.  During the timing analysis phase, signals may reach inputs
       of the gate at different arrival times.  The propagation
       delay to the output pin may depend on the n-1 arrival time
       difference...