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Browse Prior Art Database

Well-Controlled Ratio Logic Circuit

IP.com Disclosure Number: IPCOM000118531D
Original Publication Date: 1997-Mar-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 90K

Publishing Venue

IBM

Related People

Kartschoke, PD: AUTHOR [+2]

Abstract

Ratio logic circuits can evaluate faster than Complementary Metal Oxide Semiconductor (CMOS) equivalents, but the big drawback is the high power that they dissipate. One place where this high power dissipation can hurt a chip is during the burn-in testing of the chip. Burn-in testing stresses the chip at higher temperatures and higher voltages. This high voltage causes increased current to flow through these ratio logic circuits. If there were a switch to decrease the amount of current during this burn-in process, then more chips could be tested at the same time, thus increasing the through-put of this tool. Another use for being able to control the current of ratio logic circuits is the ability to decrease the power or speed up a ratio logic circuit during normal operations.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Well-Controlled Ratio Logic Circuit

      Ratio logic circuits can evaluate faster than Complementary
Metal Oxide Semiconductor (CMOS) equivalents, but the big drawback is
the high power that they dissipate.  One place where this high power
dissipation can hurt a chip is during the burn-in testing of the
chip.  Burn-in testing stresses the chip at higher temperatures and
higher voltages.  This high voltage causes increased current to flow
through these ratio logic circuits.  If there were a switch to
decrease the amount of current during this burn-in process, then more
chips could be tested at the same time, thus increasing the
through-put of this tool.  Another use for being able to control the
current of ratio logic circuits is the ability to decrease the power
or speed up a ratio logic circuit during normal operations.

      A circuit is shown here that can externally control the
strength of the load devices (PFETs are used) in ratio logic
circuits.  The PFETs used for load devices are all contained within
an NWELL.  By lowering the well voltage lower than VDD, the magnitude
of the threshold voltage of the PFET is lowered.  This in turn will
increase the current drive of the PFETs.  This lower voltage can be
used for increased performance gain.  On the other hand, if the
voltage of the NWELL could be raised, the current carrying capability
of the PFET would be reduced.  The power consumed could be
systematically reduced by a ratio logic circuit by controlling the
NWELL voltage.

      In Figs. 1, 2, and 3, three examples of the embodiment are
shown.  In Fig. 1, a low Vt (Threshold voltage) NFET is used to
control the NWELL voltage.  When the control signal is enabled, the
well voltage can be lowered from VDD to VDD-Vtb where Vtb is the body
affected threshold below VDD.  One skilled in the art of device
physics can see that the lower NWELL potential will give a larger
current flow through the PFET and because of this, we will want to
r...