Browse Prior Art Database

Fast Non-Blocking Arbiter with Fairness

IP.com Disclosure Number: IPCOM000118532D
Original Publication Date: 1997-Mar-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 88K

Publishing Venue

IBM

Related People

Johnson, DW: AUTHOR

Abstract

Disclosed is a structure for a fast 6XX Bus Master arbiter. It has these features: a small amount of logic, low latency, non-blocking, and fast cycle time.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Fast Non-Blocking Arbiter with Fairness

      Disclosed is a structure for a fast 6XX Bus Master arbiter.  It
has these features: a small amount of logic, low latency,
non-blocking, and fast cycle time.

      A scheme that grants requests quickly if there were no prior
requests and has a fairness mechanism when granting successive
requests was designed.  This scheme gives a grant in the next cycle
after an unlatched request was received.  It handles address only,
data only, and address/data requests and can have two outstanding
grants on the data bus.  It also is very "flat" for a fast cycle
time.

      It does this by breaking down processing of requests into
different tasks.  There is a separate but similar section of logic
for both address and data request processing.  The state machines are
partitioned so that Input/Output (I/O) count is low, the logic can be
implemented to run very fast, cycles are not added anywhere to
increase latency.

      Address requests are handled autonomously, so that the address
portion of the address only request or address/data request are
handled the same and are independent of what is going on with the
data request  machine.

      Data requests are handled a little differently.  Data only
requests can be handled autonomously also, but if the address request
for a given requestor is on, the address grant must be present before
the data grant can be given.  In this one case, an extra cycle of
latency is added to the bus grant so that it can be determined that
an address  has been given.  So, if an address request for a given
source is present,  it is ignored until the address grant is given.
This allows other data  grants to occur and does not allow an
address/data request to block the  data bus.  Since the address grant
for a given source must occur first  anyway, performance should not
degrade, and also since address/data requests do not block data only
requests, performance is as close to optimal as possible.

      A Grant Timing state machine determines whether a grant is
allowable in any given cycle.  For the address bus, this means a
grant is given and must be acknowledged before the next grant can be
given.  On the data bus, there can be two outstanding grants given
before the next grant.  Once an acknowledgement is seen, another
grant can be issued if there are still requests.  So the data machine
must keep count of how many grants are outstanding.  There is a mode
bit to indicate whether...