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Clock Monitoring in a Multi-Port Synchronous Optical Network/Synchronous Digital Hierarchy Physical Layer Device

IP.com Disclosure Number: IPCOM000118547D
Original Publication Date: 1997-Mar-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 143K

Publishing Venue

IBM

Related People

Herkersdorf, A: AUTHOR [+2]

Abstract

Clock monitoring is a method which is used to check whether an entire device (e.g., a chip) or a specific subunit of a device (e.g., a chiplet) is provided with an operational system clock. Clock monitoring by the control or management plane (e.g., via a microprocessor) of a network element is instrumental in order to avoid system hang-ups or potential deadlock situations in the operation among devices or among chiplets within the same device. The clock monitoring mechanism described demonstrates how the task of clock monitoring can be accomplished in an efficient and cost-effective manner for one or multiple clock islands simultaneously.

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Clock Monitoring in a Multi-Port Synchronous Optical Network/Synchronous
Digital Hierarchy Physical Layer Device

      Clock monitoring is a method which is used to check whether an
entire device (e.g., a chip) or a specific subunit of a device (e.g.,
a chiplet) is provided with an operational system clock.  Clock
monitoring by the control or management plane (e.g., via a
microprocessor) of a network element is instrumental in order to
avoid system hang-ups or potential deadlock situations in the
operation among devices or among chiplets within the same device. The
clock monitoring mechanism described  demonstrates how the task of
clock monitoring can be accomplished in an  efficient and
cost-effective manner for one or multiple clock islands
simultaneously.

      The clock monitor is applied to a multi-port Synchronous
Optical Network (SONET)/Synchronous Digital Hierarchy (SDH) framer
Physical Layer (PHY) device.  Multi-port SONET/SDH PHY devices have
the property that every receiving port has to recover its own clock
signal from the bit transition content on the serial data signal.  As
a result, the sequential control logic of every receiving port has
its own clock reference.  Therefore, it is not sufficient to just
monitor the main system clock of the device (which might be used for
data transmission) but better to have the appropriate means for
monitoring each individual receiving port clock separately.

      In general, it should be mentioned that the clock monitor
mechanism is neither restricted to SONET/SDH devices nor to
multi-port devices nor to PHY devices.  It can also be applied to any
form of communication device, be it single- or multi-port, and be it
applied at  the PHY or at a higher layer.

      For sake of simplicity, it is assumed for the following example
to have a chip with N independent clock islands, i.e., chiplets
running with an independent system clock.  Without restricting
generality, it is further assumed that the chip has some form of
control interface (e.g., a microprocessor interface) via which the
chip is initialized and controlled from some external control
instance.  The clock monitor  can be accessed via the control
interface.  Again, having the clock monitor in this example
integrated on the chip does not exclude for a different application
to have it off-chip as a separate building block.

      One solution would be to route the system clocks of all clock
islands to the clock monitoring unit and check them for periodical
transitions.  However, for clock tree balancing and route
optimization reasons, this approach is not further investigated here.

      As shown in Fig. 1, some additional hardware (one double latch)
is allocated within each individual clock island (chiplet) and
performs the clock monitoring with a handshake mechanism similar to
the traditional Request/Acknowledge.  The clock monitor asserts a
strobe on  the signal called ClockTest (Request).  In...