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Boolean Equivalence Checking on IEEE 1149.1 Test Logic

IP.com Disclosure Number: IPCOM000118600D
Original Publication Date: 1997-Apr-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 63K

Publishing Venue

IBM

Related People

Lasota, PJ: AUTHOR [+2]

Abstract

Disclosed is a solution for the Boolean Equivalency checking problem posed by the insertion of Institute of Electrical and Electronics Engineers (IEEE) 1149.1 test logic. This solution ensures that the functional state of the logic gate implementation was equivalent to the functional description. Test checking tools insured that the complete logic gate implementation of the design including the IEEE 1149.1 test logic operated correctly in all test modes.

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Boolean Equivalence Checking on IEEE 1149.1 Test Logic

      Disclosed is a solution for the Boolean Equivalency checking
problem posed by the insertion of Institute of Electrical and
Electronics Engineers (IEEE) 1149.1 test logic.  This solution
ensures that the functional state of the logic gate implementation
was equivalent to the  functional description.  Test checking tools
insured that the complete  logic gate implementation of the design
including the IEEE 1149.1 test  logic operated correctly in all test
modes.

Creation of the Logic

      Fig. 1 proposes one methodology of creating and testing a logic
design with IEEE 1149.1 logic inserted.  The functional description
is a high-level language that is used to enter the design.  Logic
synthesis is then performed on this design to create the logic gate
implementation.  The next step is where design for test synthesis
inserts the IEEE 1149.1 test logic.  It is then the designer's
responsibility to ensure that the final logic gate implementation is
functionally equivalent to the high-level design that was used to
create it.  At this point, Boolean Equivalence checking is used.
Since the design for the test synthesis step creates logic that is
not in the  high level design, equivalencies occur during the Boolean
Equivalence Checking process.

Solution

      To ensure that the functional operation of the gate level
implementation is equivalent to the high-level description, the
designer must hold th...