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Method and Apparatus for Scan Ring Alignment to Word Length

IP.com Disclosure Number: IPCOM000118685D
Original Publication Date: 1997-May-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Angelotti, FW: AUTHOR [+2]

Abstract

Scan ring lengths rarely match the word lengths used by software. As such, padding is required on every operation. This padding will vary by the length of the ring selected and the number of chips in the ring. This scheme has the hardware insert the padding based on information in the scan instruction.

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Method and Apparatus for Scan Ring Alignment to Word Length

      Scan ring lengths rarely match the word lengths used by
software.  As such, padding is required on every operation.  This
padding will vary by the length of the ring selected and the number
of chips in the ring.  This scheme has the hardware insert the
padding based on information in the scan instruction.

      The Figure shows the gating for including scan latches in the
ring based on the ring length selected.  The signals E, D, C, B, and
A refer to the last five bits of the length selected.  For example,
if the ring length is 1111 (decimal), the binary equivalent is
'10001010111'.  The last five bits make E=1, D=0, C=1, B=1, and A=1.
Following the logic in the Figure, the first multiplex (MUX) will
include one extra bit in the ring, the next will be bypassed, the
next bypassed, the next included for 8 bits, and the last bypassed.
The total  of nine bits added to 1111 results in 1120; an even factor
of 32.

      These additional bits may be added to the beginning or end of
the scan operation but should be consistent on every chip used in a
system.  Should more than one chip be included in a ring, the chips
in bypass mode can select a 32-bit bypass state to remain aligned.

      Many variations on this theme are also valid.  The padding
could simply be loaded as part of the instruction, rather than
calculated from the scan length.  While this will save hardware (the
XORs and ORs ...