Browse Prior Art Database

Circuitry to Divide a Clock by 1.5

IP.com Disclosure Number: IPCOM000118702D
Original Publication Date: 1997-May-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 37K

Publishing Venue

IBM

Related People

Benayoun, A: AUTHOR [+4]

Abstract

Disclosed is a method for a circuitry to divide a clock by 1.5.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Circuitry to Divide a Clock by 1.5

      Disclosed is a method for a circuitry to divide a clock by 1.5.

The  solution provides a non integer division by using any electronic
design.

Fig. 1 shows the components of a hardware circuit.

      Timing

      Principle of Operation

Referring to Fig. 2:
  o  the logic composed of a counter, a NAND gate and an OR
      gate is a binary counter by 3.  On each rising edge of the
      incoming clock IN the following patterns are free-running
      on the counter output pins DCBA: 0000, 0001, 0010, 0000,
      0001, 0010 .......
  o  The output Q1 of latch 1 delays the B output signal by
      half a clock because its clock input receives the
      incoming clock IN inverted
  o  The output Q2 of latch 2 delays the Q1 output signal by
      half a clock because its clock input receives the incoming
      clock IN
  o  The output Q3 of latch 3 delays the Q2 output signal by
      half a clock because its clock input receives the incoming
      clock IN inverted
  o  The clock signal generated at the output of OR2 gate
      is the incoming clock IN divided by 1.5