Synthesis Optimization by Automatic Very High Design Language Style Change
Original Publication Date: 1997-May-01
Included in the Prior Art Database: 2005-Apr-01
Benayoun, A: AUTHOR [+5]
AbstractDisclosed is a method to optimize the objective is to optimize the logic designer productivity and synthesis efficiency.
Synthesis Optimization by Automatic Very High Design
a method to optimize the objective is to optimize
the logic designer productivity and synthesis efficiency.
The advantages of the invention are:
o it is applicable to any synthesizer or technology.
o it increases the designer productivity by allowing
him to work with a high level description.
o it increases the component performances by respecting
all the designer knowledge and tricks.
Applications of the invention:
o Any Very High Design Language (VHDL) design
There are three VHDL coding styles: behavioral,
o The behavioral coding style is software-like and uses
programming structures like 'if/then/else or case'. It
is the most efficient for logic entry and simulation
productivity but the synthesis results are deeply
dependent on the synthesizer performance.
o The data-flow coding style uses arithmetic and logic
operators. It is a bit more tedious to code but very
efficient for simulation. Since it is close to the
logic description, synthesizers can easily apply a
lot of transformations to optimize the code. Timing
and placement constraints can be imposed to control
the work but all constraints cannot always be respected
because it is not easy to prevent a synthesizer to work
on such described logic parts: constraints may be
set on nets which have disappeared during a previous
optimization phase. Therefore, designer tricks may
disappear in the output netlist because of resources
o The structural coding style allows to assign "don't touch"
constraints on logic blocks that will be respected by the
synthesizer. It consists in describing the logic at its
lowest level by "instantiating" the technology basic
gates. The problem is that such a description is extremely
tedious and long and creates a large amount of data to
handle. In addition, it cannot be used for a VLSI chip due
to the number of basic cells to describe (in fact, it
corresponds to the netlist...).
is a program that allows the designer to code a
data-flow description and automatically transforms this description
into a structural one with all the synthesizer necessary commands.
1. converts the statements that the designer wants to preserve