Browse Prior Art Database

Method of Cubing Different Size Chips

IP.com Disclosure Number: IPCOM000118719D
Original Publication Date: 1997-Jun-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 6 page(s) / 130K

Publishing Venue

IBM

Related People

Palagonia, AM: AUTHOR

Abstract

Disclosed is a method of forming a cube using different size chips. To date, cubes have been formed from the exact same size chips. Many applications for cube technology exist that require cubing of different chip types, such as "camera" cubes; however, special designs, often wasteful of silicon area, need be created such that all chips of different functions have the same physical size, precluding the use of off-the-shelf chips having just the added processing required for cube technology.

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Method of Cubing Different Size Chips

      Disclosed is a method of forming a cube using different size
chips.  To date, cubes have been formed from the exact same size
chips.  Many applications for cube technology exist that require
cubing of different chip types, such as "camera" cubes; however,
special designs, often wasteful of silicon area, need be created such
that all chips of different functions have the same physical size,
precluding the use of off-the-shelf chips having just the added
processing required for cube technology.

      Cube technology entails printing special interconnect lines on
the top surface of chip (Fig. 1A), coating the chip with heat
sensitive adhesive, stacking the chips front to back in a jig, and
pressing them together at a temperature sufficient to cure the
adhesive.  Each combination of chip/interconnect wiring/adhesive
forms a "course" within the stack.  Afterwards, the face of the cube
is polished exposing the end of the interconnects and various wiring
schemes applied to this face (Fig. 1B).

      The cube of the invention is made up of full size chips
(Fig. 2A) in some courses, and smaller chips next to dummy chips in
other courses (Figs. 2B and 2C).  The active chips in these courses
have the same interconnect/adhesive layers as the full size chips,
while the dummy chips are blank silicon, having only the adhesive, or
the adhesive and perhaps some dummy interconnect wiring depending
upon the size of the dummy chip for alignment and thermal stressing
reason.  The finished stacked cube is shown in Fig. 2D.  In Fig. 2C,
the small active chip shares one lateral dimension in common with the
full size chips, while in Fig. 2C, the small active chip has no
common lateral dimension with the full size chips.  Both the small
active chip and the dummy chip(s) are the same thickness.

      While the s...