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Data Line Driver Circuit for Active Matrix Liquid Crystal Display

IP.com Disclosure Number: IPCOM000118722D
Original Publication Date: 1997-Jun-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 103K

Publishing Venue

IBM

Related People

Schlig, ES: AUTHOR

Abstract

Disclosed are circuits that extend the area of applicability of charge-metering sampled-staircase data line driver circuits (1-3). Refer to (3) for details of charge metering and the data line driver application. This disclosure covers modifications to the two stages of the analog subsystem of the driver. The track/hold stage is modified for operation in the high voltage mode with minimum power supply voltage range, and the output or analog latch stage is modified for demultiplexed operation, in which each driver output serves multiple data lines in time sequence, with minimal additional components. The two modified stages may be used independently or in combination.

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Data Line Driver Circuit for Active Matrix Liquid Crystal Display

      Disclosed are circuits that extend the area of applicability of
charge-metering sampled-staircase data line driver circuits (1-3).
Refer to (3) for details of charge metering and the data line driver
application.  This disclosure covers modifications to the two stages
of the analog subsystem of the driver.  The track/hold stage is
modified for operation in the high voltage mode with minimum power
supply voltage range, and the output or analog latch stage is
modified for demultiplexed operation, in which each driver output
serves multiple data lines in time sequence, with minimal additional
components.  The two modified stages may be used independently or in
combination.  High voltage mode means that the two inversion states
required by the liquid crystal, one below (-) and one above (+) the
common electrode voltage, are both directly generated by the driver
circuit.  The new circuits are shown in Fig. 1.  A timing diagram of
the track/hold stage in each of the two inversion states is shown in
Fig. 2.  No threshold correcting reference voltage generator (3) is
shown because the intended application is one in which all required
data line drivers are integrated into the same chip, so threshold
variation is negligible.  If needed, it may be incorporated.  The
digital subsystem of the driver is conventional for sampled-staircase
drivers and so is not shown.

      The track/hold stage of Fig. 1 is an inverting charge-metering
sampling circuit.  In the prior art, such circuits use a power supply
voltage range that substantially exceeds the output voltage range.
This is because the voltage ranges of the input staircase waveform
and the output must be disjoint.  The new circuit avoids that problem
by including two charge-metering transistors, NMOS 1 which supplies
the output in the + inversion state and PMOS 2 which serves the -
inversion state.  The input staircase for the NMOS has approximately
the same voltage range as the output when the PMOS is used, and the
input staircase for the PMOS approximately the same as the output for
the NMOS, so for this design the overall output range of the
track/hold stage is 2 to 12 V for a power supply range of 0 to 12 V.
The second stage drops the voltage by 1 V, so the final output
voltage range is 1 to 11 V.  When NMOS 1 is active, PMOS...