Browse Prior Art Database

Battery-Backup Method for Dram-Based Memory Systems

IP.com Disclosure Number: IPCOM000118727D
Original Publication Date: 1997-Jun-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Katayama, Y: AUTHOR

Abstract

Disclosed is a DRAM-based memory system that can enhance the refresh cycle of DRAMs, thus realizing a high-density and low-cost battery-backup memory system. The adaptive DRAM refresh scheme with on-chip error correction/checking and compression circuits dramatically reduces the refresh power.

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Battery-Backup Method for Dram-Based Memory Systems

      Disclosed is a DRAM-based memory system that can enhance the
refresh cycle of DRAMs, thus realizing a high-density and low-cost
battery-backup memory system.  The adaptive DRAM refresh scheme with
on-chip error correction/checking and compression circuits
dramatically reduces the refresh power.

      Figs. 1 and 2 show the operation of the proposed memory device
and a block diagram of the proposed device, respectively.  The device
works as an ordinary DRAM-based memory system in the normal mode with
ordinary DRAM interface.  In the suspend mode, it performs the
following steps:
  1.  The on-chip logic circuitry performs error coding (both
       checking and correction) and compression of the stored
       data.  This operation can be performed either once for
       the entire memory or many times after dividing the memory
       into multiple segments.
  2.  The timer triggers the refresh operation for a certain
       segment with only error checking.  If no error is found,
       the next refresh for that segment will be performed with
       a prolonged refresh cycle.
  3.  A SRAM is used for storing the refresh cycle interval for
       different segments, as well as for storing the temporary
       data during the error coding and compression operation.

      The disclosed memory system has an additional advantage in
terms of the da...