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In-Rush Current Reduce Circuit

IP.com Disclosure Number: IPCOM000118731D
Original Publication Date: 1997-Jun-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 44K

Publishing Venue

IBM

Related People

Sakaba, S: AUTHOR

Abstract

In a Personal Computer (PC) Card, a small circuit is provided for effectively reducing in-rush current on a power supply line.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

In-Rush Current Reduce Circuit

      In a Personal Computer (PC) Card, a small circuit is provided
for effectively reducing in-rush current on a power supply line.

      In Fig. 1, the area enclosed with the broken line shows the
in-rush current reduce circuit which is located between the input
power pin and the main circuit.  The differential circuit for the
input voltage  (Vcc) is composed of C and R, and Q is the P-channel
FET.

      Referring to Figs. 1 and 2, the signal (W1) is the differential
wave form of Vcc and is connected to the GATE of the FET.  The
resistance between the SOURCE and the DRAIN of the FET (Rsd) depends
on the voltage  between the SOURCE and the GATE of the FET (Vsg = Vcc
- W1), as shown in Fig. 3.  Therefore, Rsd is high at the moment when
Vcc is supplied (Vsg = 0V), then decreases gradually according to
Vsg, and at last when  Vsg = Vcc, it becomes very low.  The in-rush
current for the main circuit  (I1) does not flow at a time when Vcc
is supplied but flows gradually according to Vsg.  The peak current
can be reduced effectively compared  with I2 that shows the in-rush
current without the circuit.