Browse Prior Art Database

Tracing of Large Amounts of Data by Using Main Memory as a Trace Buffer

IP.com Disclosure Number: IPCOM000118732D
Original Publication Date: 1997-Jun-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 151K

Publishing Venue

IBM

Related People

Goldrian, G: AUTHOR [+2]

Abstract

Tracing units in Very Large Scale Integration (VLSI) chips are very common. They are used for debug purposes of the chip logic and, if possible, for analysis of problems in a complex system. However, the usage of these tracing units is limited by the amount of data which can be stored in the tracing buffer. Since only a small area of a chip can be spent for service support, the size of the tracing buffer is very often too small, especially in complex error situations.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 42% of the total text.

Tracing of Large Amounts of Data by Using Main Memory as a Trace
Buffer

      Tracing units in Very Large Scale Integration (VLSI) chips are
very common.  They are used for debug purposes of the chip logic and,
if possible, for analysis of problems in a complex system.  However,
the usage of these tracing units is limited by the amount of data
which can be stored in the tracing buffer.  Since only a small area
of a chip can be spent for service support, the size of the tracing
buffer is very often too small, especially in complex error
situations.

      The idea is to extend the tracing capability with a Direct
Memory Access (DMA) and a simple data compression logic.  The DMA is
the means to support a huge tracing buffer in the S/390 memory where
the size of this tracing buffer is programmable by a control command
to the Memory Bus Adapter (MBA).  With this capability, all selected
events within more than one second can be traced, allowing the
analysis of complex problems, even in a parallel Sysplex environment.
The compression logic, on the other hand, is the means to allow the
tracing of logic signals every clock cycle of the VLSI chip and still
use the huge tracing buffer in the memory.  With this feature,
complex problems  in the attachment of the Self Timed Interfaces
(STI) links in the MBA can be analyzed because of the practically
unlimited size of the tracing  buffer.  Only a small speed matching
buffer (256 bytes), a simple DMA,  and a compression logic is
required to build the high performance tracing  unit.

      The Tracing Unit in the MBA is intended for debug of MBA
hardware, microcode, and software.  To achieve this goal, the Tracing
Unit has to be able to trace each clock cycle in a selected
functional unit (for logic debug) and, on the other hand, it should
be able to record all significant events over a long period of time.
Since hardware  debug and software debug do not occur at the same
time, the Tracing Unit  can be switched to different modes, allowing
the high frequency of tracing entries for hardware debug and the
significantly lower frequency  of tracing entries for microcode and
software debug.

The Tracing Unit in MBA supports two different tracing modes:
  o  Cycle Trace
  o  Event Trace

      Cycle Trace is the recording of every clock cycle of selected
logic signals.  Although the time period to be covered by tracing is
relatively small, the size of the tracing buffer has still to be big
because the frequency of trace entries is very high.  Since there is
only room in the MBA for a tracing buffer with the size of less than
1kB, a Growable Register Array (GRA) is selected which can hold only
two Memory Lines (256 bytes) and is used as a Ping Pong Buffer.
During the time one half of this buffer is recording the tracing
entries, the  other half of the buffer unloads the collected data to
the respective speed matching buffer of the MBA, from where it is
stored to main memory. ...