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One-Cycle Simulation of Master-Slave Logic in the General Case

IP.com Disclosure Number: IPCOM000118735D
Original Publication Date: 1997-Jun-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 94K

Publishing Venue

IBM

Related People

-W Anderson, H: AUTHOR [+3]

Abstract

Logic-Simulation using the 'Cycle-Simulation' algorithm has two phases per cycle: 1. evaluation of the logic. 2. fetch the values at the inputs of the storing elements and store them, this is called Latch-Update.

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One-Cycle Simulation of Master-Slave Logic in the General Case

      Logic-Simulation using the 'Cycle-Simulation' algorithm has two
phases per cycle:
  1.  evaluation of the logic.
  2.  fetch the values at the inputs of the storing elements
       and store them, this is called Latch-Update.

      Normally, pairs of storing elements (master-slave-flipflops)
are used in synchronous logic to avoid feedback loops.  The first
storing element (master-latch) of such a pair will be triggered by
the master(M)-clock in the normal case.  The second storing element
(slave-latch) will then be triggered by the slave(S)-clock, which
will be switched on when the master-clock goes off and vice versa.
Usually, the slave-latch (triggered by the slave-clock) gets its
value directly  and exclusively from the master-latch (triggered by
the master-clock).

      To avoid feedback loops, there must be no path from the input
of a latch to the output of a latch that is triggered by the same
clock.  But it is allowed that a master-latch is triggered by a
slave-clock, and it is possible to insert logic in a path between the
outputs of a latch that is triggered by the master-clock and the
inputs of latch that is triggered by the slave-clock.

Cycle-simulation has the following behavior, caused by these two
clock signals:
  1.  evaluation of the logic
  2.  latch-update triggered by master-clock
  3.  evaluation of the logic
  4.  latch-update triggered by slave-clock

      For one 'logical' simulation cycle (shown by the state of the
slave-latches), there are two cycle-simulation steps necessary.  But
theoretically it is possible to do a one-cycle simulation.

Based on the assumption, that:
  1.  the data-inputs of all latches triggered by the
       master-clock depend only on latches triggered by the
       slave-clock
  2.  the data-inputs of all latches triggered by the slave-clock
       depend only on latches triggered by the master-clock

The logic will have the following behavior:
  input_masters=f2 (Zustand_slaves); masters(i+1)
     =input_masters(i);
  input_slaves=f1 (Zustand_masters); slaves(i+1)
     =input_slaves(i);
  f1() and f2() are any functions and i is the cycle counter.

The following table shows some simulation cycles:

                            (Image Omitted)

  Table: State Table for Two-Cycle Simulation M = state of all
          master latches  S = state of all slave

The columns A and B show the state transitions defined by f1() and
f2().

Column C shows, that state S(2) can be reached from state S(0), S(4)
from S(2) ,...

      In column D, the...