Browse Prior Art Database

Asynchronous Interface Design using a Funneling First In/First Out

IP.com Disclosure Number: IPCOM000118736D
Original Publication Date: 1997-Jun-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 102K

Publishing Venue

IBM

Related People

Gregerson, JC: AUTHOR [+2]

Abstract

Disclosed is a method for asynchronous communication where both the width of the Input/Output (I/O) data and its frequencies can vary widely without causing changes to the design. With one side of the logic wider then the other, the communications logic is said to "funnel" data. The problem of providing a link between two separately clocked systems of wildly differing frequencies and bus widths is to guarantee proper sampling of the asynchronous signals. The pattern (i.e., Grey Code) transmitted across the asynchronous boundary must be sufficient to provide a sufficient pulse width and accommodate multiple increments for funneling functions.

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Asynchronous Interface Design using a Funneling First In/First Out

      Disclosed is a method for asynchronous communication where both
the width of the Input/Output (I/O) data and its frequencies can vary
widely without causing changes to the design.  With one side of the
logic wider then the other, the communications logic is said to
"funnel" data.  The problem of providing a link between two
separately clocked systems of wildly differing frequencies and bus
widths is to guarantee  proper sampling of the asynchronous signals.
The pattern (i.e., Grey Code) transmitted across the asynchronous
boundary must be sufficient to provide a sufficient pulse width and
accommodate multiple increments  for funneling functions.

      The following solution is general and unique.  The fundamental
design consists of parallel dual ported arrays with read and write
pointers provided by opposite clock boundaries.  The generation of
First In/First Out (FIFO) flags (full, empty, almost full, etc.) is
done by comparing the pointers passed across the asynchronous
boundary.  The data is written at the same time the write pointer is
incremented and sampling on the read clock guarantees data stability
by gating.  A 2-to-1 funneling FIFO was designed which passed a
pointer across the asynchronous boundary that provided a minimum 1.5
cycle pulse when counting by two.  The pointer consists of a shifting
pattern on its low order bits and the typical grey code pattern on
its high order bits.  Addressing of the FIFO is done through a decode
of the pointer, and flag generation is done with a decode that
accommodates two bits changing across the asynchronous boundary.

      This solution can be applied to implementations with varied
clock frequencies and bus widths:
                 N >= Cy/Cx * 1.5 * Bx/By >= 1
           where N  = size of the shifting pattern required.
                 Cy = lower freq cy...