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Enhanced Arbitration Scheme to Increase Peripheral Component Interconnect Bus Performance during Delay Transactions Handled by a Personal Component Interconnect-to-Personal Component Interconnect Bridge

IP.com Disclosure Number: IPCOM000118768D
Original Publication Date: 1997-Jun-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 78K

Publishing Venue

IBM

Related People

Ephstein, M: AUTHOR [+3]

Abstract

Delayed transaction termination is used by Peripheral Component Interconnect (PCI) targets that cannot complete the initial data phase within the requirements of the PCI specification*. In general, a PCI-to-PCI bridge may choose to handle multiple transactions to improve system performance.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Enhanced Arbitration Scheme to Increase Peripheral Component Interconnect
Bus Performance during Delay Transactions Handled by a Personal Component
Interconnect-to-Personal Component Interconnect Bridge

      Delayed transaction termination is used by Peripheral Component
Interconnect (PCI) targets that cannot complete the initial data
phase within the requirements of the PCI specification*.  In general,
a PCI-to-PCI bridge may choose to handle multiple transactions to
improve system performance.

      One advantage of a delayed transaction is that the bus is not
held in wait-states while completing an access to a slow device.
While the originating master rearbitrates for the bus, other bus
masters are  allowed to use the bus bandwidth that would normally be
wasted.

      During the first phase, the master generates a transaction on
the bus, the bridge decodes the access, latches the information
required to complete the access, and terminates the request with
retry. According  to PCI 2.1 rev specification, an initiator master
that was retried on the  first data phase must repeat the request
until the request completes. At  this point, the bridge independently
completes the request on the destination bus using the latched
information from the delayed request.  The result of completing the
delayed request on the destination  bus produces a delayed
completion.  The bridge stores the delayed completion until the
master repeats the initial request.

      Completing a cross bridge delay transaction may take the bridge
a considerable number of cycles.  If, during this time, the master
wins the arbitration, the bridge must terminate the access with
retry; hence,  resulting in decreased bus performance.  By preventing
the master from  winning bus ownership while the delayed transaction
is not completed, other bus masters can use the bus bandwidth.

      Both a protocol for crossing the bridge and an arbitration
scheme are proposed.  Operating under this protocol and arbitration
scheme, the initi...