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Decode Technique for Fast Data Transfers

IP.com Disclosure Number: IPCOM000118786D
Original Publication Date: 1997-Jul-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 109K

Publishing Venue

IBM

Related People

Ellis, WF: AUTHOR [+3]

Abstract

Within a computer, systems blocks of data are moved from one location in physical memory to another location in physical memory. These blocks are of a fixed size (typically 4 Kbytes) representing a logical 'page'. Movement of these data pages within memory are currently performed by means of a sequence of low level data move operations. Typically, each individual data move operation moves 4 bytes of data by first reading the 4 bytes of data from one part of physical memory and then writing the data into the new location. This operation is repeated, 4 bytes at a time, until all the data has been moved. Assuming a 4 byte memory interface, to move a 4 Kbytes page would require a total of 1,000 data read and 1,000 data write operations. Using 90nsec memory, this operation would take approximately 140 microsec.

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This is the abbreviated version, containing approximately 52% of the total text.

Decode Technique for Fast Data Transfers

      Within a computer, systems blocks of data are moved from
one location in physical memory to another location in physical
memory.  These blocks are of a fixed size (typically 4 Kbytes)
representing a logical 'page'.  Movement of these data pages within
memory are currently performed by means of a sequence of low level
data move operations.  Typically, each individual data move operation
moves 4 bytes of data by first reading the 4 bytes of data from one
part of physical memory and then writing the data into the new
location. This  operation is repeated, 4 bytes at a time, until all
the data has been moved.  Assuming a 4 byte memory interface, to move
a 4 Kbytes page would require a total of 1,000 data read and 1,000
data write operations.  Using 90nsec memory, this operation would
take approximately  140 microsec.

      Disclosed here is the concept of 'virtual' data page
moves.  The 'virtual' page move is performed by the use of writeable
address registers within the memory controller.  Rather than
physically moving a page of data, the equivalent function is
performed by simply changing the contents of a pair of address
registers within the memory controller.

      Fig. 1 illustrates the system configuration of a processor,
memory controller, and physical memory which is composed of Dynamic
Random Access Memories (DRAMs).  Within the memory controller are a
set of address registers.  These address registers map the physical
addresses generated by the processor into the actual addresses
(CAS/RAS signals) used to access the DRAMS.  Each address register
contains two fields:
  o  The Physical Address Field (PAF).  This is the address
      generated by the processor.  The PAF field of the register
      contains the starting address of the physical page.
  o  The DRAM Address Field (DAF).  This is the actual location
      in the memory array where the data page is stored.  This
      field contains the CAS/RAS signals necessary to address
      the starting location of the page stored in the DRAM array.

Each address register is programmable and is initially set up as part
of system initialization.

      A single (byte or word) data move operation is to be performed
in the following manner.  The physical address from the data move
instruction is used to map against the PAFs of the address
registers....