Browse Prior Art Database

Peripheral Component Interconnect-Lite Bus Interface Design

IP.com Disclosure Number: IPCOM000118790D
Original Publication Date: 1997-Jul-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 85K

Publishing Venue

IBM

Related People

Abdelnour, GM: AUTHOR [+2]

Abstract

Disclosed is a solution which provides a low-cost, efficient method for attaching data storage to a Peripheral Component Interconnect (PCI) bus and separating it from the main processor storage.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Peripheral Component Interconnect-Lite Bus Interface Design

      Disclosed is a solution which provides a low-cost, efficient
method for attaching data storage to a Peripheral Component
Interconnect (PCI) bus and separating it from the main processor
storage.

      The PCI bus has been architected as a high-speed interface
between a microprocessor and peripheral functions.  Because the PCI
standard has been approved and accepted, there are many peripheral
functions that have been designed to the PCI standard, and they are
available on the market today.

      When designing efficient high-speed processor subsystem, the
executable instruction storage is separated from the data storage
from the peripheral functions.  In a data analysis environment, data
received from the external world is stored in random access memory
separate from the processor subsystem.  A low-cost efficient method
is needed to transfer data from the peripheral interfaces into data
storage over the PCI bus yet isolated from the main processor
subsystem.

      Two design trade-offs make this low-cost and efficient.  Since
the PCI bus uses only one interface to transfer both address and
data, the implementation of an address counter with byte offsets is
normally required.  The PCI-lite implementation limits the transfers
to four fullword transfers.  This transfer rate is adequate for
communication network transfers.  The implementation of a 32-bit
address is now reduced to a register plus a two-bit counter.  Second,
fullword transfers are only allowed except for the last transfer of a
message.  This eliminates the byte alignment problem which requires a
large number of circuits to re-align fullwords in memory that are
split across two PCI bus transfers.  This implementation does not
limit the master or slave operation of peripheral devices.  However,
it does limit the number of devices that can be attached with an
arbi...