Browse Prior Art Database

Programmable Code Execution Address Limit Protection

IP.com Disclosure Number: IPCOM000118809D
Original Publication Date: 1997-Jul-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 128K

Publishing Venue

IBM

Related People

Kammerer, RJ: AUTHOR [+3]

Abstract

Disclosed is a protection circuit that limits instruction fetch operations to a predefined area of memory, segments a memory device (i.e., EEPROM) into code and data spaces, allows for varying code space sizes due to microcode updates, and provides a latched error output signal when invalid code fetch operations are detected.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 48% of the total text.

Programmable Code Execution Address Limit Protection

      Disclosed is a protection circuit that limits instruction fetch
operations to a predefined area of memory, segments a memory device
(i.e., EEPROM) into code and data spaces, allows for varying code
space sizes due to microcode updates, and provides a latched error
output signal when invalid code fetch operations are detected.

      As shown in the Figure, the code address protection circuitry
monitors instruction fetches to ensure that they are within a valid
range of code addresses.  Three compare functions indicate that the
addresses are within specific ranges; additional signals are used to
gate these outputs and provide a valid period for updating the
+Error_Out signal.  Once asserted, the error signal is held active
until the CodeTop register is read or the -Reset signal is activated.

      The +Error_Out signal is connected to the NonMaskable Interrupt
(NMI) pin of the microprocessor.  When +Error_Out is activated, a
nonmaskable interrupt is generated.  This stops the invalid
instruction fetch data from being executed, forcing the
microprocessor to run its NMI routine instead.

      The intended application for this circuit employs a
microprocessor with sixteen data bits and twenty external address
bits (Address(19:0)) which define a 1M byte linear memory space.  In
this particular application a EEPROM is used to store code, as well
as some bytes of permanent data.  The address space for this EEPROM
is from 'C0000'X to 'FFFFF'X.  All external addresses below 'C0000'X
define memory space for data storage or memory mapped I/O devices.
An additional requirement of our application is that the address
space from  'F2000'X through 'F2FFF'X be dedicated for certain key
microprocessor resources.  This memory area contains the interrupt
vectors, configuration registers, and the reset starting address.
Instruction fetch accesses to this region must be allowed, even if
the address is beyond the area of valid code storage.

      Circuit Operation

      Address signals 19 through 12 are monitored by three positive
active comparator circuits.  The OR/AND combination produces a high
level output when an error condition is detected.  Also connected to
this AND gate are the +Read and +Inst signals.  These two signals
ensure that the AND gate can only be activated during an instruction
fetch operation.

      The first comparator is activated whenever Address(19:12) is
not equal to 'F2'X.  This comparator signal is '0' whenever the
address is between 'F2000'X and 'F2FFF'X, which gates off the AND
output and blocks the error signal.  This comparator allows
instruction fetches within the special area of memory space.

      The second comparator verifies that Address(19:18) are both at
a high logic level.  If one or both of these address bits are '0',
then the output of this comparator would be set.  This comparator
verifies that the instruction...