Browse Prior Art Database

Minimum Size Complementary Metal Oxide Semiconductor Buffer Circuit

IP.com Disclosure Number: IPCOM000118829D
Original Publication Date: 1997-Jul-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Storino, SN: AUTHOR [+2]

Abstract

Disclosed is a small buffer circuit that was needed for easy layout and easy insertion into custom Very-Large-Scale Integration (VLSI) macros.

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This is the abbreviated version, containing approximately 100% of the total text.

Minimum Size Complementary Metal Oxide Semiconductor Buffer Circuit

      Disclosed is a small buffer circuit that was needed for easy
layout and easy insertion into custom Very-Large-Scale Integration
(VLSI) macros.

      The minimum size buffer circuit is made out of five
transistors, as shown in the Figure.  There are two PFETs and three
NFETs.  The two PFETs and two of the NFETs are configured just like
two inverters in a standard buffer.  The difference from a standard
buffer is that the sources of the two NFETs are tied to the drain of
the third NFET rather than ground.  The source of the third NFET is
then tied to ground.  Its gate is tied to Vdd so that it is
permanently on.  This arrangement of transistors allows the PFETs to
be implemented at minimum size.  All three NFETs are at minimum as
well.

      The third NFET is required for the entire buffer.  This third
NFET could, in fact, be used by other like buffers if they cascaded
in a string such that the sources of all the inverter NFETs were tied
to the drain of this one NFET.