Browse Prior Art Database

Boundary-Scan Configurations

IP.com Disclosure Number: IPCOM000118833D
Original Publication Date: 1997-Jul-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 104K

Publishing Venue

IBM

Related People

Douskey, SM: AUTHOR [+3]

Abstract

Boundary scan has become common in Application Specific Integrated Circuit (ASIC) design. There are three basic structures that can be combined to make many other useful configurations. This disclosure describes those structures and some other variations beyond those basics.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Boundary-Scan Configurations

      Boundary scan has become common in Application Specific
Integrated Circuit (ASIC) design.  There are three basic structures
that can be combined to make many other useful configurations.  This
disclosure describes those structures and some other variations
beyond those basics.

Boundary scan latches configurations come in three basic forms:
  o  "functional" latches in series with the data path.
  o  "flush-thru" latches in series with the data path.
  o  "multiplexed" (MUXed) latches parallel to the data path.

      In all cases, they are designed to sample the data from inside
the chip and drive data to the chip internal logic for internal
testing and/or to drive and sample data from other chips or a tester
an external  driver/receiver/interconnect test.  Only the MUXed
version is fully Institute of Electrical and Electronics Engineering
(IEEE) 1149.1 compliant, though the others are very useful as well.

      Fig. 1 shows the basic structure of a flush common Input/Output
(I/O) boundary scan configuration.  Dl, El, and Rl represent storage
elements.  The DCLK, ECLK, and RCLK clocks all go to '1' when the
system is in operation but are gated clocks for internal and external
testing.

      Fig. 1 also can represent the functional version of the Common
I/O (CIO).  The DCLK, ECLK, and RCLK clocks are then functional
clocks during system operation but will be gated during internal and
external testing.

 Fig. 1 CIO Boundary Scan and IO Configuration (Flush or Functional)

      Fig. 2 represents the basic MUX version of the Common IO.  The
DCLK, ECLK, and RCLK clocks are then only used for internal and
external testing.  The DG, EG, and RG are MUX gating signals that
select the path from the storage element when in the appropriate test
mode.

      Mixing the three styles of receiver boundaries with the
three driver and three enable styles result in 27 boundary scan
configurations.  Any of the MUX storage elements can also be made
flush or functional before the MUX, allowing the designer to use the
storage element and the MUX functionally.  This now defines 125
different versions.

      Dropping the Driver and Enable for Receiver only versions
creates five more (though leaving Dl and El storage elements in the
scan path may simplify test pattern generation).  Dropping the
Receiver for a Driver only creates 25 more (again leaving the Rl in
the scan path  m...