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Data Transfer Rate Reduction for Liquid Crystal Display Source Driver Integrated Circuit Using Memory Block Addressing

IP.com Disclosure Number: IPCOM000118841D
Original Publication Date: 1997-Aug-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 102K

Publishing Venue

IBM

Related People

Kimura, Y: AUTHOR [+3]

Abstract

Disclosed is a method using memory block addressing to reduce data transfer rate. Fig. 1 shows timing charts and a required memory size. (1) in Fig. 1 shows inline row data. W0 through W9 are row data to be written each source driver S0 through S9 in Fig. 2. As shown in (2) and (3), W0 through W9 data are split in odd data and even data. Consequently, R0 through R9 data can be read in half transfer rate against each W0 through W9 data shown in (4) and (5). (6) and (7) in Fig. 1 shows the required memory size for even and odd drivers in chronological order. The memory is used as First In First Out (FIFO) memory. Each maximum memory size is needed for a half of Mtab. Mtab is defined as total row data size of each driver. For example, if the driver has 384 output and 18bits data, Mtab is 6912(bits). (8) in Fig.

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Data Transfer Rate Reduction for Liquid Crystal Display Source Driver
Integrated Circuit Using Memory Block Addressing

      Disclosed is a method using memory block addressing to reduce
data transfer rate.  Fig. 1 shows timing charts and a required memory
size.  (1) in Fig. 1 shows inline row data.  W0 through W9 are row
data to be written each source driver S0 through S9 in Fig. 2.  As
shown in (2) and (3), W0 through W9 data are split in odd data and
even data.  Consequently, R0 through R9 data can be read in half
transfer rate  against each W0 through W9 data shown in (4) and (5).
(6) and (7) in Fig. 1 shows the required memory size for even and odd
drivers in chronological order.  The memory is used as First In First
Out (FIFO) memory.  Each maximum memory size is needed for a half of
Mtab.  Mtab is defined as total row data size of each driver.  For
example, if the  driver has 384 output and 18bits data, Mtab is
6912(bits).  (8) in Fig. 1 shows total memory size of (6) and (7) in
chronological order.  Its maximum memory size is 5/8 Mtab.

      Fig. 2 shows block diagram of this method.  This block diagram
consists of 5 blocks of Random Access Memory (RAM) and a read control
circuit for block addressing and a write one.  The RAM blocks size is
1/8 Mtab each.  The row data W0 through W9 are written into B0
through B4.  The data can be read from B0 through B4 in a half
transfer rate against writing transfer rate.  The B0 through B4 data
are spl...