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Topology for Accessing Buffered Data in a Two-Chip Memory Controller Design

IP.com Disclosure Number: IPCOM000118882D
Original Publication Date: 1997-Aug-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 120K

Publishing Venue

IBM

Related People

Maule, WE: AUTHOR [+2]

Abstract

As bus frequencies increase for chip-to-chip communications in system designs, it becomes extremely important to minimize, if not eliminate, logic gate delays from these paths. A good design practice is to have all external chip signals be launched directly from a latch and to receive all chip input signals directly into a latch. This practice, however, sometimes presents unique problems in maintaining architectural bus protocol requirements. Such was the case in the Control Chip/Dataflow Chip (CTL/DFL) memory controller design. CTL receives addresses from the connecting processors and sends command busses to DFL to source or sink data to the various data busses in the system. A typical system topology using the CTL/DFL chipset is shown in Fig. 1. All chip Input/Output (I/O) were latch bounded in the design.

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This is the abbreviated version, containing approximately 52% of the total text.

Topology for Accessing Buffered Data in a Two-Chip Memory Controller
Design

      As bus frequencies increase for chip-to-chip communications in
system designs, it becomes extremely important to minimize, if not
eliminate, logic gate delays from these paths.  A good design
practice is to have all external chip signals be launched directly
from a latch  and to receive all chip input signals directly into a
latch.  This practice, however, sometimes presents unique problems in
maintaining architectural bus protocol requirements.  Such was the
case in the Control Chip/Dataflow Chip (CTL/DFL) memory controller
design.  CTL receives addresses from the connecting processors and
sends command busses to DFL to source or sink data to the various
data busses in the  system.  A typical system topology using the
CTL/DFL chipset is shown in Fig. 1.  All chip Input/Output (I/O) were
latch bounded in the design.

      The invention describes a unique topology used to preserve
timing integrity of signals used to access data from a register file
without adding additional cycles of latency to the first data
access.  Timing Diagram 1 reflects system requirements for data
access from DFL.

      For illustrative purposes, it can be assumed that a register
file in DFL can buffer several cache lines of data.  The RD_BUF# bus
specifies which cache line in the register file is to be accessed.
The CTL chip can request that the data from one of these cache lines
be sent  to DFL's DATA_OUT bus by signalling a read on the SYS_READ
line and sending the cache line buffer number on the RD_BUF# bus.
The CTL chip  must in turn arbitrate for the data bus before the data
packet can be presented.  Once arbitration is complete, CTL signals
DFL to provide the  stream of data by sending the BUS_GRANT signal.
The BUS_GRANT signal will remain active to indicate the length of the
data transfer from DFL  (i.e., number of beats).  All signals from
CTL to DFL must be latched on  DFL before use in order to maintain
the bus frequency requirement. Also,  as seen in the timing diagram
above, the first piece of data must be present on the DATA_OUT bus 1
cycle after BUS_GRANT is provided. This  presents a unique problem
given the topology shown in Fig. 2 in that the  first piece of data
must already be out of the register file waiting in  DFL's output
latch (OUT_L) in the same cycle that BUS_GRANT_L (the latched version
of BUS_GRANT) becomes available.  For all remaining data  beats, the
problem of how to start incrementing the register file access
counter also posed proble...