Browse Prior Art Database

Reduction of Interprocessor Communications Latency via Sensor Data Caching

IP.com Disclosure Number: IPCOM000118903D
Original Publication Date: 1997-Sep-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 90K

Publishing Venue

IBM

Related People

Hamilton, RA: AUTHOR [+3]

Abstract

Disclosed is a method of reducing interprocessor communication latency. This particular methodology is most relevant to cases in which one processor is engaged in hardware and/or environmental monitoring activity.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Reduction of Interprocessor Communications Latency via Sensor Data
Caching

      Disclosed is a method of reducing interprocessor communication
latency.  This particular methodology is most relevant to cases in
which one processor is engaged in hardware and/or environmental
monitoring activity.

      In this disclosure, "primary processor" refers to a processor
issuing a request for data.  "Responding processor" refers to the one
servicing this request.

      In modern computer systems, the issue of interprocessor latency
is a concern, especially in cases where system performance is
directly impacted by such delays.  The latencies can be nuisances, in
those cases  where the user might notice or somehow experience the
delay, OR under exceptional circumstances, the delays can result in
degraded system integrity.  An example of the latter is the case
where the interprocessor  communication has commenced and is followed
immediately by an unrelated  critical error.  Normally, processors
take certain actions to prevent data loss in these cases.  However,
in the event that the ongoing data  request cannot be interrupted,
the primary processor must simply wait for the response before
servicing the error.  If the error represents an  imminent power
failure, the result can be corrupted or lost data, as the  primary
processor is unable to take the proper shutdown procedures prior  to
power loss.

      The latencies in this example can be precipitated by a number
of events: the fundamental speed of the responding processor; the
possibility that the responding processor is temporarily occupied
with another task and, thus, is unable to respond; or the possibility
that the request itself incurs such delays that the response cannot
come as  quickly as needed by the primary processor.

      This disclosure focuses on the last scenario, that of how to
overcome latencies imposed by the nature of the tasks themselves and
specifically, the case when these long-lead tasks deal with the
reading of data from remote sensors.

      A specific incidence of this problem arose on the IBM RS/6000*,
for communications running between an abstraction layer on the
primary processor (RTAS or Runtime Abstraction Layer) and the
product's Service  Processor.  In the embodiment described here, a
method was developed for  ensuring that long-lead sensor data
collection times were not experienced  by the primary processor.  In
turn, the ability of the primary processor  to perf...