Browse Prior Art Database

Corrective Device for Data Recovery in Synchronous Serial Link

IP.com Disclosure Number: IPCOM000118913D
Original Publication Date: 1997-Sep-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 82K

Publishing Venue

IBM

Related People

LeMaut, F: AUTHOR [+2]

Abstract

Disclosed is a correcting device used to allow a synchronous data receiver to sample proper data regardless of the delay introduced by the transmission carrier. The clock signal is generated by the Receiver and provided to the Transmitter. The device does not perform data oversampling.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Corrective Device for Data Recovery in Synchronous Serial Link

      Disclosed is a correcting device used to allow a synchronous
data receiver to sample proper data regardless of the delay
introduced by the transmission carrier.  The clock signal is
generated by the Receiver and provided to the Transmitter.  The
device does not perform  data oversampling.

      In synchronous data exchange, data is generally sent by the
Transmitter on one edge of the clock signal and sampled by the
Receiver on the opposite edge.  Depending on the delay introduced by
logic circuitry and transmission carrier, the phase relationship
between data  and sampling clock may be such that data can be lost,
precisely when data transition occurs in coincidence with the clock
sampling edge.

      The purpose of that disclosed device is to track the delay
between the data transition and the clock sampling edge and perform a
correction in the data path to allow proper sampling by the
Receiver.  The maximum latency introduced by the correction is half
the sampling clock period.

The correcting circuit is composed of three major functions:
   a.  Resampling of the incoming data on the opposite edge of
        the Receiver sampling edge.
   b.  Multiplexing between resampled incoming data (function a.)
        or original incoming data.
   c.  Tracking of phase relationship between data transition and
        clock sampling edge in order to generate the multiplexer
        command.

      Functions a. and b. will not be developed in this article
because they do not present any complexity.  The originality of this
device resides in function c. explained hereafter.

      Thanks to a delay line and simple logic, two windows are
generated:  one centered on the trailing and the second centered on
the falling sampling clock edge.  These windows are used to track...