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Method and Apparatus for Forcing a Translation Hit Based on the Processor Operation

IP.com Disclosure Number: IPCOM000118916D
Original Publication Date: 1997-Sep-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 87K

Publishing Venue

IBM

Related People

Steenburgh, JA: AUTHOR [+2]

Abstract

The processor in this example has a single interface between the processing and the storage control units for translatable commands, register operations, input/output operations, and other non-translatable instructions. The translation logic indicates to the processor using the translation miss signal whether or not the translation of the Effective Address sent by the processor was successful. Many of the processor operations in this example architecture do not require translation to execute and the translation miss signal was required to be inactive, indicating a translation hit. As a consequence of a single interface, the hardware in the processor did not expect any translation to occur for these operations.

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Method and Apparatus for Forcing a Translation Hit Based on the Processor
Operation

      The processor in this example has a single interface between
the processing and the storage control units for translatable
commands, register operations, input/output operations, and other
non-translatable instructions.  The translation logic indicates to
the processor using the translation miss signal whether or not the
translation of the Effective Address sent by the processor was
successful.  Many of the processor operations in this example
architecture do not require translation to execute and the
translation miss signal was required to  be inactive, indicating a
translation hit.  As a consequence of a single  interface, the
hardware in the processor did not expect any translation  to occur
for these operations.  The solution used to fix this problem was  to
force the translation miss signal to be inactive each time one of
the operations that did not need translation was executed.

      Address Translation for this example architecture is the
translation of a 64-bit Effective Address (EA) to an 80-bit Virtual
Address (VA) to a 40-bit Real Address (RA).  The address lengths
discussed here are specific to this example.  The translation process
translates an EA to a RA if translation is successful.  Translation
would be unsuccessful if one of the following had happened during the
translation process:
  1.  There was no matching entry found in the Segment Lookaside
       Buffer (SLB) array.
  2.  There was no matching entry found in the Translation
       Lookaside Buffer (TLB) array.
  3.  The Tag Summary or Change Bit was not set in the matching
       TLB entry.
  4.  A storage fault was detected during translation.
  5.  There was a parity error detected in one or more of the
       classes at the TLB address that was accessed during the
       translation process.

      If translation is unsuccessful due to one or more of these
conditions, then the translation miss signal is activated.  This
indicates to the processing unit that the translation logic has more
work to do before the Effective Address that it was given can be
translated.

      When the processing unit executes a command that is
non-translatable the address that is provided with the command does
not go through the translation process from EA to VA to RA.  A
non-translatable command has an address that either is not used or is
used directly to address the system memory, an input or output
device, or a register.  Therefore, the conditions that could cause a
translation miss do not apply to the non-translatable commands and
the translation  miss signal should be inactive.

      The solution used to fix this problem with the shared interface
for command execution that was used in this example implementation
involved clearing out all of the above conditions that could cause a
translation miss when one of the non...