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Performance Optimized Routing Based on Net Groups

IP.com Disclosure Number: IPCOM000118922D
Original Publication Date: 1997-Sep-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Harrer, H: AUTHOR [+4]

Abstract

Disclosed is a new router methodology for an automatic generation of Release Interface Tape (RIT) data, which are the source for manufacturing Multi-Chip Module (MCM) and card wiring structures. The methodology is based on a performance optimized approach, where the wiring nets are categorized in different classes. The router is controlled by a wiring restriction in the form of a minimum and maximum net length for each type. As for a large number of nets, it is not possible to specify a rule on a per net basis. The router input is structured by the net groups. Hence, the router can be forced to wire the time critical nets nearly within manhattan distance, while the wirability is kept by having looser restrictions for the noncritical nets.

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Performance Optimized Routing Based on Net Groups

      Disclosed is a new router methodology for an automatic
generation of Release Interface Tape (RIT) data, which are the source
for manufacturing Multi-Chip Module (MCM) and card wiring structures.
The methodology is based on a performance optimized approach, where
the wiring nets are categorized in different classes.  The router is
controlled by a wiring restriction in the form of a minimum and
maximum net length for each type.  As for a large number of nets, it
is not possible to specify a rule on a per net basis.  The router
input is structured by the net groups.  Hence, the router can be
forced to wire  the time critical nets nearly within manhattan
distance, while the wirability is kept by having looser restrictions
for the noncritical nets.

      Today's routers have sophisticated algorithms for wiring within
minimum distance.  Wiring rules can be specified by net weights or
length restrictions for a min/max length, which have to be specified
for each net.  However, it is not possible for the router to wire a
structured input that is based on performance criteria.  For complex
packaging structures, the wiring on a single module (e.g., a card,
board, or MCM) depends on the net type, the chip logic, and the
geometry of the other modules.

Wiring Methodology

The Figure gives a sketch of the router methodology.

The router performs the wiring from four sources:
  1.  The Packaging High Structure Design Language (PHSDL) file
       describes the logic connections of the module, which can be
       a multi-chip module, a processor board, or a memory card and
       specifies the net group.  The net group depends on the on
       chip and off chip structure, as well as on the timing
       requirements.  It gives a measurement of how much wiring
       can be spent on the module.  The nets are described in a
       compromised f...