Browse Prior Art Database

Technique for Wafer-Scale Integration

IP.com Disclosure Number: IPCOM000118947D
Original Publication Date: 1997-Sep-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Hofstee, HP: AUTHOR

Abstract

Disclosed is a technique for wafer-scale integration where: 1. A design is partitioned into a set of components placed in a plane. Inter-component wires are designed such that inter-component wiring on a complete wafer can be fabricated with high yield. 2. Flip-chip bonding pads are specified for each component such that all inter-component wires originate and terminate in a bonding pad within a component. Furthermore, a mechanism must exist for disconnecting a component from its pads (fuse or laser disconnect, for example). 3. Both the designed wafers (*) and their mirror-image are fabricated. 4. The components on each wafer are burned in (if required) and tested. 5.

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Technique for Wafer-Scale Integration

      Disclosed is a technique for wafer-scale integration where:
  1.  A design is partitioned into a set of components placed
       in a plane.  Inter-component wires are designed such that
       inter-component wiring on a complete wafer can be fabricated
       with high yield.
  2.  Flip-chip bonding pads are specified for each component such
       that all inter-component wires originate and terminate in a
       bonding pad within a component.  Furthermore, a mechanism
       must exist for disconnecting a component from its pads
       (fuse or laser disconnect, for example).
  3.  Both the designed wafers (*) and their mirror-image are
       fabricated.
  4.  The components on each wafer are burned in (if required)
       and tested.
  5.  Wafers with a large percentage of faulty components are
       diced up and the faulty components are discarded.
  6.  Faulty components on the remaining wafers are disconnected
       from their pads.
  7.  Components of the opposite chirality of those disconnected
       are flip-chip attached to the pads of the disconnected
       components.
  Reference
  (*) Patent No. 3984860