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Method and Apparatus for Real Address Parity Generation for Block Address Translation Entries

IP.com Disclosure Number: IPCOM000118949D
Original Publication Date: 1997-Sep-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Steenburgh, JA: AUTHOR [+2]

Abstract

A method of generating parity over 28 bits of a Real Address (RA) was required for the Block Address Translation (BAT) Content Addressable Memory (CAM). The parity generation could not be done by conventional generation methods since 11 bits of the Real Address contained in the Block Real Page Number (BRPN) in the BAT CAM are variable and depend on the 11-bit Block Length (BL) field also contained in the BAT CAM and the Effective Address (EA) being translated. The solution used was to do part of the parity generation before storing the BRPN in the BAT CAM and the rest when the BAT CAM was read out as a result of translation.

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Method and Apparatus for Real Address Parity Generation for Block
Address Translation Entries

      A method of generating parity over 28 bits of a Real Address
(RA) was required for the Block Address Translation (BAT) Content
Addressable Memory (CAM).  The parity generation could not be done by
conventional generation methods since 11 bits of the Real Address
contained in the Block Real Page Number (BRPN) in the BAT CAM are
variable and depend on the 11-bit Block Length (BL) field also
contained in the BAT CAM and the Effective Address (EA) being
translated.  The solution used was to do part of the parity
generation before storing the  BRPN in the BAT CAM and the rest when
the BAT CAM was read out as a result of translation.

      Address Translation for the implementation, described in this
disclosure using Block Address Translation, is the translation of a
64-bit Effective Address (EA) to a 40-bit Real Address (RA).  The
address lengths discussed here are specific to this example.  For the
purposes of this discussion, all addresses will be assumed to be 80
bits in length numbered from 0 to 79.  The addresses of less than the
80 bits will be right justified with the Most Significant Bits (MSBs)
filled in with zeros.  For example, the 16 MSBs of the 80-bit EA will
be zero, and the 64-bit EA will occupy bit positions 16-79.  A
logical extension of this example would be to say that any bit length
for any of the addresses is possible with this disclosure.

      Translation in the BAT is described here.  Any one entry in the
BAT CAM contains bits 16-62 of the EA and bits 40-62 of the BRPN.
The BAT RA(40-62) is equivalent to RA(40-62).  If the 47 bits of the
EA in  the BAT CAM match the corresponding 47 bits of the incoming
EA, then a  match has been found.  The BAT RA contained in the
matching BAT CAM entry is read out and appended with bits 63-79 of
the EA to form the 80-bit RA to address system memo...