Browse Prior Art Database

360 Degree Phase Shifting Clock Output

IP.com Disclosure Number: IPCOM000118961D
Original Publication Date: 1997-Oct-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Johnson, DW: AUTHOR

Abstract

Disclosed is a method for producing phase-shifted clocks. This scheme uses a combination of a digital delay line and a mux to skew a given clock input to a latch, whose output becomes a clock output for the chip. Multiple sets of muxes and latches then provide multiple clock outputs, each of which can be skewed relative to the others. The phase step that each can be skewed is dependent on the delay step through the delay line.

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360 Degree Phase Shifting Clock Output

      Disclosed is a method for producing phase-shifted clocks.  This
scheme uses a combination of a digital delay line and a mux to skew a
given clock input to a latch, whose output becomes a clock output for
the chip.  Multiple sets of muxes and latches then provide multiple
clock outputs, each of which can be skewed relative to the others.
The phase step that each can be skewed is dependent on the delay step
through the delay line.

      The data input to the output latches comes from a common
flip-flop latch.  In this way, it is guaranteed that all outputs are
in-phase.  If there were multiple flip-flops, like one for each
output, the phase relationship between the outputs would be more
difficult to guarantee.  For each output, a mux with an inverter on
one leg allows the  latch data input to be inverted, or normal,
giving a 180 degree phase shift.

      By combining the phase shift and the inverter, a wide range of
output phases are possible, over 360 degrees, if the depth of the
delay line is sufficient relative to the operating frequency.  The
delay line  is common to all clock outputs.  For each clock group,
there is a mux to  select the phase delay and a mux to select whether
the data input is inverted.

      A fixed output can also exist by using one of the delay ports
(selected to have some relationship to the varying outputs) and
feeding it directly to the latch output.