Browse Prior Art Database

Gigabit Speed Multi-Protocol Chip and Adapters for Network Computing

IP.com Disclosure Number: IPCOM000118966D
Original Publication Date: 1997-Oct-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 102K

Publishing Venue

IBM

Related People

Noel, FE: AUTHOR [+3]

Abstract

Disclosed is a method for supporting multiple protocols (Asynchronous Transfer Mode (ATM) at either 1.244 Gbps, ATM at 1.0 Gbps, or Gigabit Ethernet at 1.0 Gbps speeds) in the same hardware chip. Autosensing of which protocol is present on the line is integral to the chip/microcode using a first order test of PHY control characters, as well as a second order test using an algorithm to determine which protocol is present on the line. An integrated bridging function between Gigabit Ethernet frames and ATM cells allows the chip to support frame-to-cell or cell-to-frame conversion.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Gigabit Speed Multi-Protocol Chip and Adapters for Network Computing

      Disclosed is a method for supporting multiple protocols
(Asynchronous Transfer Mode (ATM) at either 1.244 Gbps, ATM at 1.0
Gbps, or Gigabit Ethernet at 1.0 Gbps speeds) in the same hardware
chip.  Autosensing of which protocol is present on the line is
integral to the chip/microcode using a first order test of PHY
control characters,  as well as a second order test using an
algorithm to determine which protocol is present on the line.  An
integrated bridging function between  Gigabit Ethernet frames and ATM
cells allows the chip to support frame-to-cell or cell-to-frame
conversion.

      In the proposed Gigabit Ethernet draft standard (IEEE Draft
P802.3z), the standard PHY interface uses the Fibre Channel Standard
(FCS) "ANSI Fibre Channel Physical and Signalling Interface (FC-PH)"
at 1.25 Gbps, yielding 1.0 Gbps with 8B/10B encoding.

      The FCS PHY can be used for any type of data stream (for
example, ATM cell, Ethernet or Token Ring frame).  ATM cells can be
run over the FCS PHY at Gigabit speeds, so long as endpoints are
compatible (for example, within a campus) or at OC-x speeds (for
example, OC-12 at  1.244 Gbps).

      This disclosure describes a common communication chip and
adapter that can operate in either of the following modes:
  o  1 Gbps Fiber Channel Standard (FCS)
  o  1 Gbps Ethernet
  o  1 Gbps ATM
  o  1.244 Gbps ATM
  o  1 Gbps Ethernet with ATM cell conversion
  o  1 Gbps Ethernet with encapsulated ATM cells as well as having an
autosense function to accurately detect Ethernet frames or ATM cells
on the physical interface.

      Installation and setup procedures could be used to configure
the adapter or switch blade using this technology for one of these
modes, or a better alternative described here would use an
autosensing mechanism in the adapter to detect whether ATM cells or
Gigabit Ethernet  frames were arriving over the physical interface;
and to then operate in  the detected protocol mode.

      The Figure illustrates a multi-protocol gigabit-per-second
chip, capable of supporting (in this case) either ATM cells or
Ethernet frames.  Token-ring could also be an option.

      A cell conversion function in the chip can be used in a switch
blade that incorporates this chip to convert Ethernet frames to ATM
cells (and vice versa) for a device such as a switch with ATM
cell-based backplane.  In this case, both device drivers would work
in conjunction  with the switch blade.

      Autosensing can be done at either the PHY layer and/or the
protocol layer.  Examples of autosensing are given for both cases.

Three types of detection can be implemented at the PHY layer:
  1.  Autosense native FCS.  This entails searching for and
       detecting K28.5 control characters (and...