Browse Prior Art Database

Latency Optimized Interrupt to S/390 Parallel Processors

IP.com Disclosure Number: IPCOM000118984D
Original Publication Date: 1997-Oct-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 158K

Publishing Venue

IBM

Related People

Fritz, R: AUTHOR [+2]

Abstract

The amount of processing power a S/390* Parallel Sysplex can deliver depends on how many S/390 Central Electronic Complexes (CECs) can be coupled and how efficiently this can be done. This is defined by the coupling efficiency of a given system.

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Latency Optimized Interrupt to S/390 Parallel Processors

      The amount of processing power a S/390* Parallel Sysplex can
deliver depends on how many S/390 Central Electronic Complexes (CECs)
can be coupled and how efficiently this can be done.  This is defined
by the coupling efficiency of a given system.

      The coupling efficiency of a S/390 Parallel Sysplex depends on
how fast an average message between a coupled S/390 and a Coupling
Facility can be processed.  The following parameters contribute to
the amount of the message processing time:
  o  Software path length in S/390 to send the message and
      receive the response.
  o  Microcode path length in Coupling Facility to process
      the message and send the response.
  o  Microcode path length in S/390 to send the message and
      receive the response.
  o  Physical Link performance.  The time required to transport
      the message and the response via the link between S/390 and
      Coupling Facility.
  o  The amount of latency between hardware, microcode, and
      software for the receipt of a message and of a response.

      Disclosed is a method on how the latency between hardware and
microcode can be improved.  Currently, the System Assist Processor
(SAP) in the S/390 is polling the Memory Bus Adapter (MBA) to find
new requests  from the Input/Output (I/O) Subsystem.  This method
generates a high latency because the SAP will only look for new work
until it is free to  do so.  Even if it is free, there is still a
significant latency caused  by the low repetition rate of the
polling.  To avoid an overload of the  Bus Switching Network (BSN), a
high polling rate is not possible.

      Currently, we have the possibility of activating an attention
line from the MBA to the SAP to resolve the bus utilization problem.
However, this is only a partial improvement of the latency between
hardware and microcode.  There is still the problem that the SAP
may be busy with a process which is not interruptable and which may
take more than 1,000 processor cycles.

      Latency Optimized Interrupt

      The idea is to enable the MBA to generate a control command
to a Processor Unit (PU) which is either idling or waiting for an
event.  And, if no PU is idling, then the control should be directed
to a PU which is not busy with a long routine which is not
interruptable.

      To achieve that the control to the PU has to produce an
interrupt, the selection of the PU has to be performed by hardware
based on the state of the PUs which has to be indicated in the MBA.
This can  be performed by state bits for each PU which will be
updated whenever a  sense or control operation from a PU is directed
to the MBA.

      The invention idea does not depend on a special control from
the MBA.  However, the MBA_SigP_Request has been defined, because of
the current limitation in the wiring capability of the proc...