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Merging Cache and Storage Controller on One Multi-Function Chip

IP.com Disclosure Number: IPCOM000119012D
Original Publication Date: 1997-Oct-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 110K

Publishing Venue

IBM

Related People

Goldrian, G: AUTHOR

Abstract

In a Symmetrical Multi-Processor System (SMP), two or more processors are connected to a common memory with an interconnection network consisting of many Very Large Scale Integration (VLSI) logic chips. They support a multi-processor protocol with its switch and cache functions. A typical SMP structure is shown in Fig. 1. A number of processors, which have an internal level 1 cache (L1), are connected via a level 2 cache (L2) to a shared level 2.5 cache (L2.5). The high bandwidth requirement of the buses between the processors and the memory and the limited number of the available signal pins leads to this approach of clustered processors.

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Merging Cache and Storage Controller on One Multi-Function Chip

      In a Symmetrical Multi-Processor System (SMP), two or more
processors are connected to a common memory with an interconnection
network consisting of many Very Large Scale Integration (VLSI) logic
chips.  They support a multi-processor protocol with its switch and
cache functions.  A typical SMP structure is shown in Fig. 1.  A
number of processors, which have an internal level 1 cache (L1), are
connected via a level 2 cache (L2) to a shared level 2.5 cache
(L2.5).  The high bandwidth requirement of the buses between the
processors and the memory and the limited number of the available
signal pins leads to this approach of clustered processors.

      The invention idea is to build a multi-function chip which
combines all required functions to connect the processors with the
DRAM chips of a common memory.  This multi-function chip (SMP-chip)
is to be  placed, together with the processors, on a multi-chip
module.  This multi-chip module will be able to directly access the
DRAM chips of the  memory.

The major functions of this chip are:
  o  Shared level 2 cache for all processors (L2).
  o  Storage Controller (STC) contained on said multi-function
      SMP chip.
  o  Connection of the reusable memory cards to said
      multi-function chip.

What is new in this approach is the integrated STC.  This allows to
optimize the memory card for low latency and high bandwidth in the
data transfer by adding special address drivers and data multiplexor
chips to the DRAMs and by moving all PU technology dependent logic
from the card.  This scheme allows to reuse the expensive memory card
for several  processor generations.

      Combining all SMP interconnection functions in one chip type
allows to further reduce the latency to the DRAM chips in the memory
cards.  But, the major advantage is that this scheme allows that the
expensive memory card can be reused in future SMP without major
impact on the SMP performance.  The memory cards can now be built
with optimized  high performance address driver chips.  Also, for the
data multiplexor  functions, current low cost technology can be
selected.  These can be smal...