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Interrupt Sampling for an Interrupt Controller in a Peripheral Component Interconnect Host Bridge

IP.com Disclosure Number: IPCOM000119020D
Original Publication Date: 1997-Oct-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Guthrie, GL: AUTHOR [+2]

Abstract

Disclosed is a method for minimizing the pin count needed for sampling Interrupts when implementing an Interrupt controller in an Application Specific Integrated Circuit (ASIC).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Interrupt Sampling for an Interrupt Controller in a Peripheral Component
Interconnect Host Bridge

      Disclosed is a method for minimizing the pin count needed for
sampling Interrupts when implementing an Interrupt controller in an
Application Specific Integrated Circuit (ASIC).

      Implementing an Interrupt Controller(IntC) function within an
ASIC, like that found in a Peripheral Component Interconnect* (PCI)
Host Bridge (PHB), is typically a pin intensive task.  This presents
a problem  for most Input/Output (I/O) type ASICs since they are
typically constrained when it comes to the number of I/O pins
available.

      The PCI bus, as with some other I/O busses, defines interrupts
to be level sensitive and asynchronous.  In order to save pins in the
IntC, a simple Multiplexer (MUX) can be used external to the IntC to
sample the Interrupts.  The IntC controls the select lines to the
external MUX and switches the selects (synchronous to the IntC clock)
to sample the next set of Interrupts.  Because the Interrupts are
level sensitive, the IntC can rotate though all the Interrupts
feeding the MUX without missing any active interrupts.  This saves
the IntC from having to dedicate one pin for each interrupt.  Because
the Interrupts are asynchronous to the IntC clock, the speed at which
the external MUX selects switch can be a multiple of the IntC clock
frequency (i.e., the MUX selects may switch at 1/2,r 1/4 the speed of
the internal IntC clock in order to match the speed of the external
MUXes).

      The Figure shows how the external Interrupt...