Browse Prior Art Database

Load with Intent to Modify

IP.com Disclosure Number: IPCOM000119024D
Original Publication Date: 1997-Oct-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Hardell Jr, WR: AUTHOR [+2]

Abstract

In most multiprocessor systems, cache coherency is enforced by a processor/bus protocol. Most protocols are similar to MESI. In MESI, a cache line is in the state modified, exclusive, shared, or invalid. This protocol is efficient for sharing of cache lines. Usually, when a processor wants a cache line that other processors have a copy of, the processor wanting the data issues a READ to the system. This activity is usually started by a LOAD instruction. For example: Processor#0 Processor#1 ----------- ----------- Owns cache line 'A' (state is exclusive) Reads cache line 'A' (Load instruction) (state now shared) (state shared)

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Load with Intent to Modify

      In most multiprocessor systems, cache coherency is enforced
by a processor/bus protocol.  Most protocols are similar to MESI.  In
MESI, a cache line is in the state modified, exclusive, shared, or
invalid.  This protocol is efficient for sharing of cache lines.
Usually, when a processor wants a cache line that other processors
have a copy of, the processor wanting the data issues a READ to the
system.  This activity is usually started by a LOAD instruction.  For
example:
  Processor#0             Processor#1
  -----------             -----------
  Owns cache line 'A'
  (state is exclusive)
                          Reads cache line 'A' (Load instruction)
  (state now shared)      (state shared)

      This protocol is less efficient for typical operations such as
checking a variable modifying it.  This is because the variable is
loaded (making the cache line shared), then a state transition must
be made to make the line exclusive on the processor doing the
increment.  For example:
  Processor#0             Processor#1
  -----------             -----------
  Owns cache line 'A'
  (state is exclusive)
                          Reads cache line 'A' (Load instruction)
  (state shared)          (state shared)
                          Writes to cache line (Store instruction)
                          **must send bus op to other
                            processors which may have the line**
  (state becomes          (state becomes exclusive->modified)
 ...