Browse Prior Art Database

Connecting an Interbus Master to the Peripheral Component Interconnect Bus

IP.com Disclosure Number: IPCOM000119043D
Original Publication Date: 1997-Nov-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Neumann, M: AUTHOR [+4]

Abstract

Disclosed is a method of connecting an InterBus Master to the Peripheral Component Interconnect (PCI) Bus.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Connecting an Interbus Master to the Peripheral Component Interconnect
Bus

      Disclosed is a method of connecting an InterBus Master to the
Peripheral Component Interconnect (PCI) Bus.

      The layout has been performed using standard
components.  However, it includes an Erasable Programmable Logic
Device (EPLD), which contains the complete controlling of the PCI
connection, i.e., logical and temporal characteristics of the circuit
which are defined by this circuit technique (Figure).

      Both parts are independently clocked, the InterBus Master with
standardized 16 MHz and the PCI connection with 33 MHz.  Therefore,
there is only one connection to the controller of the InterBus
Master, which  is used only in case defects will arise.  Thus, this
is the kind of Interrupt System which starts specific predetermined
actions.

      The complete data transfer to the InterBus Master and from the
InterBus Master to the PCI Bus connection is done by means of a Dual
Port Memory (DPM) that can be written and read from both sides
independently and asynchronously.  The necessary handshaking is
guaranteed via special  bits in reserved DPM registers using software
inquiry.

      The interface to the PCI bus is realized by using a PCI bridge
module.  This module corresponds to the PCI Local Bus Specification
and covers the whole PCI Bus protocol.