Browse Prior Art Database

Address Selection to Maximize Data Bus Utilization of Synchronous DRAMs

IP.com Disclosure Number: IPCOM000119058D
Original Publication Date: 1997-Nov-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 119K

Publishing Venue

IBM

Related People

Genz, RH: AUTHOR [+2]

Abstract

Disclosed is a method for making the least significant bits of a cache line address to be the bank selects of a DRAM so that back-to-back data on the data bus can be achieved.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 62% of the total text.

Address Selection to Maximize Data Bus Utilization of Synchronous
DRAMs

      Disclosed is a method for making the least significant bits
of a cache line address to be the bank selects of a DRAM so that
back-to-back data on the data bus can be achieved.

      Commands to successive addresses to the same bank of SDRAM
(Synchronous DRAM) requires that the precharge time be met before
another command can be issued.  Waiting for the precharge time
results in dead  cycles on the memory data bus.  However, alternate
banks of a SDRAM can be overlapped and back-to-back data on the
memory data bus can be achieved.

      Data transfers between cache and main memory are frequently
several cache lines at a time.  Each cache line requires a separate
command with a unique address.  If the least significant bits of the
cache line address are selected to be the address of the bank selects
of a SDRAM, then alternate banks will be selected and result in
maximum bus utilization because alternate banks can be overlapped and
not have to  wait for the precharge time requirement of the same
bank. Back-to-back  data can be achieved on the memory data bus with
alternate bank selection, thereby achieving maximum bus utilization.

      An example of addressing is as follows.  For a cache line of 64
bytes and a word width of 16 bytes, then the four least significant
bits of an address field would select the bytes in the word.  The
next two least significant bits would selec...