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Techniques to take Instruction Level Traces in an SMP Environment

IP.com Disclosure Number: IPCOM000119098D
Original Publication Date: 1997-Nov-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 4 page(s) / 87K

Publishing Venue

IBM

Related People

Smolders, LR: AUTHOR

Abstract

Disclosed are the techniques used in ctrace, an instruction level tracing tool, to support SMP environments.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Techniques to take Instruction Level Traces in an SMP Environment

      Disclosed are the techniques used in ctrace, an instruction
level tracing tool, to support SMP environments.

      In order to be able to take traces in an SMP environment,
several problems have to be resolved.  First, per processor saving
areas are needed.  Second, per processor trace buffers are necessary,
and finally, since timestamps are not available, another technique is
needed to be able to synchronize the different traces produced by
each CPU.

      A per processor saving area is provided by allocating one
pinned saving area per processor and saving pointers to them in a
communication area accessible to the kernel flih and to the tracing
code.  A common data area containing the data which can be shared by
all the CPUs is also allocated and a pointer to it is saved in each
of the per CPU saving areas.

      The communication area has two words.  One is the address
of the tracing code, and the next one is the address of the saving
areas.  The saving areas appear as shown below:
  saving_area(0)--> points to (1)
  saving_area(1)--> points to (2)
  saving_area(2)--> points to (3)
  saving_area(3)--> points to (4)
  (1): beginning of saving area for cpu 0
  <--- saving area -->
  (2): beginning of saving area for cpu 1
  <--- saving area -->
  (3): beginning of saving area for cpu 2
  <--- saving area -->
  (4): beginning of saving area for cpu 3
  <--- saving area -->
  end of saving_area

      The AIX* kernel maintains a per processor data area and keeps a
pointer to it in the special register SPRG0.  It also maintains a
pointer to the current thread in SPRG2.

      To be able to use the technique described below in ctrace SMP,
one word is added to the ppda, and a global pointer (to the
communication area) is exported to the kernel.

When a trace interruption occurs, the following technique is used:
  1.  One register is saved in SPRG2 (had the current thread
       pointer)
  2.  the register is loaded with the ppda pointer (from SPRG0)
  3.  r3 is saved at ppda->trace_save_register
  4.  restore SPRG2 from ppda->curthread
  5.  get cpu id fro...