Browse Prior Art Database

Chip Wiring Algorithm for Yield Improvement

IP.com Disclosure Number: IPCOM000119103D
Original Publication Date: 1997-Nov-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Mashima, I: AUTHOR

Abstract

The proposed algorithm is to maintain the metal fill-rate at the target density all through the Large Scale Integration (LSI) design process without affecting the extracted capacitance data. Accordingly, the LSI timing verification process will be drastically shortened. The proposed algorithm will take the following steps: 1. Specify the target metal fill-rate for each metal layer. 2. The wiring tool will perform the pseudo wiring along with the wiring channels for each metal layer to meet the specified metal fill-rate. 3. The wiring tool will perform the actual wiring along with the wiring channels based on the given logic netlist. 4.

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Chip Wiring Algorithm for Yield Improvement

      The proposed algorithm is to maintain the metal fill-rate at
the target density all through the Large Scale Integration (LSI)
design process without affecting the extracted capacitance data.
Accordingly, the LSI timing verification process will be drastically
shortened. The  proposed algorithm will take the following steps:
  1.  Specify the target metal fill-rate for each metal layer.
  2.  The wiring tool will perform the pseudo wiring along with
       the wiring channels for each metal layer to meet the
       specified metal fill-rate.
  3.  The wiring tool will perform the actual wiring along with
       the wiring channels based on the given logic netlist.
  4.  In case the actual wires and pseudo wires overlap at
       Step 3, the overlapped pseudo wires will be stripped off
       and space trimming will be done so that the actual wires
       and pseudo wires do not short each other.
  5.  Extract the capacitance and resistance data.
  6.  Repeat from step 2 when redoing placement and
       actual wiring after the timing verification.

      With this method, the metal fill-rate is kept at the target
value through the design process; therefore, the extracted
capacitance does not change during the design process.  Old
algorithms add the pseudo  wires at the last step up to the target
fill-rate by changing the capacitance data.  The capacitance chang...