Browse Prior Art Database

Transition Records for Tracing Program Flows on Amazon and POWERPC Machines

IP.com Disclosure Number: IPCOM000119107D
Original Publication Date: 1997-Nov-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Smolders, LR: AUTHOR

Abstract

Disclosed is a method to deal with program flow discontinuities when using Amazon* or POWERPC* branch trace exception mechanism. This disclosure is a modified version of [*]. The technique described in (*) does not work on the Amazon family of processors because they do not reset the Machine State Register bits controlling the Performance Monitor after a synchronous exception as the execution of a system call or a page fault. Since the controlling bits do not get reset, the hardware monitor continues to count; and there is no clear transition between user and kernel flow of execution, which means that the "in-transition" as described in (*) will not work.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 55% of the total text.

Transition Records for Tracing Program Flows on Amazon and POWERPC
Machines

      Disclosed is a method to deal with program flow discontinuities
when using Amazon* or POWERPC* branch trace exception mechanism.
This disclosure is a modified version of [*].  The technique
described in (*)  does not work on the Amazon family of processors
because they do not reset the Machine State Register bits controlling
the Performance Monitor  after a synchronous exception as the
execution of a system call or a page  fault.  Since the controlling
bits do not get reset, the hardware monitor  continues to count; and
there is no clear transition between user and kernel flow of
execution, which means that the "in-transition" as described in (*)
will not work.

      The disclosed technique works on both POWERPC and Amazon
families of processors because it is independent of the msr bits
setting upon exception.  Introduced is a modified "in-transition"
where a marker for the trace exception handler is not only set, but
also the address before entering the kernel.  This address is saved
by the AIX* kernel just after the exception (and before the trace can
be restarted).  The transition code simply copies the address in the
same area as the resume address is put on out-transitions (the marker
for in and out transitions is different).  Since the address before
entering the kernel is the last instruction of the last user level
basic block, the trace processing code can easily cal...