Browse Prior Art Database

Cache Blocks/Lines by Stride

IP.com Disclosure Number: IPCOM000119210D
Original Publication Date: 1996-Mar-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Peterson, MJ: AUTHOR

Abstract

Caches often contain data that is not needed since they normally hold data in sequential address blocks. The concept of this disclosure is to hold only the needed information, thus making better use of the cache (effectively making the cache larger).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 64% of the total text.

Cache Blocks/Lines by Stride

      Caches often contain data that is not needed since they
normally hold data in sequential address blocks.  The concept of this
disclosure is to hold only the needed information, thus making better
use of the cache (effectively making the cache larger).

      At this time, many designers of process chips are working
on techniques to identify a "stride" in the addresses accessing the
memory space of a computer.  They can use this stride to predict what
data will be needed and prefetch it.

      Since caches are organized in consecutive blocks of address
space, the processor may have to access a large amount of unused data
in order to get the predicted data in the cache.

      The solution to this problem is to organize the cache as blocks
of strided addresses rather than blocks of consecutive addresses.
Each cache block would have it's starting address and an appropriate
stride.

      For example, a cache block might normally be organized as 128
consecutive bytes at address A.  If stride prediction determines that
only every other byte is needed (or word or doubleword, etc.), then
this block is stored at address A with a stride of 2.  Every other
byte of the sequential block of 128 bytes is stored in the first half
of the cache block and the other half would be filled with every
other byte from the A+1 seq block.

      The hit/miss determination and "data steering logic" would have
to take the stride into acco...