Browse Prior Art Database

Wafer Level Test And Burn-In

IP.com Disclosure Number: IPCOM000119211D
Original Publication Date: 1991-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Butkus, BJ: AUTHOR [+2]

Abstract

By distributing power and ground plus four signal lines in kerf regions between chips, testing and burn-in becomes possible before chip separation and module packaging. Power lines are connected to chips via fusible links and short signal lines from the kerf signal bus onto each chip are high resistance connections. Thus, chip failures are tolerated without losing test functionality of good chips on a wafer. All connections from kerf buses to chips are made of non-corrosive materials, e.g., a metal silicide.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 61% of the total text.

Wafer Level Test And Burn-In

      By distributing power and ground plus four signal lines
in kerf regions between chips, testing and burn-in becomes possible
before chip separation and module packaging.  Power lines are
connected to chips via fusible links and short signal lines from the
kerf signal bus onto each chip are high resistance connections.
Thus, chip failures are tolerated without losing test functionality
of good chips on a wafer. All connections from kerf buses to chips
are made of non-corrosive materials, e.g., a metal silicide.

      Referring to the figure, ground and voltage supply (VDD) kerf
buses 2 are disposed one over the other, providing capacitive
decoupling.  Bus lines 2 in the kerf may be of high conductivity,
corrosive metal.  Short lines 4 from kerf buses to chip 6 connections
are non- corrosive material or a passivating coating must be applied
after chips are separated.  Lines 4 also are shaped to have a fuse
region of small cross-sectional area.  Thus, a bad chip drawing
excessive current blows the fuse link, thus avoiding overloading the
power bus.

      Four high conductivity signal bus lines 8 are shown disposed
orthogonally to power bus lines 4.  Short, bus-to-chip connectors 10
are of material and physical dimensions to provide electrical
resistance in these connectors which prevents a bad chip from
overloading signal bus lines.  Connectors 10 are also of
non-corrosive material or must be passivated after chip separati...