Browse Prior Art Database

In Situ Dynamic Fault Detection

IP.com Disclosure Number: IPCOM000119216D
Original Publication Date: 1991-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 3 page(s) / 95K

Publishing Venue

IBM

Related People

Larsen, WR: AUTHOR [+4]

Abstract

LSSD testable, "fault detection" logic circuits used in the Holbrook and Safford programs, are described which allow high frequency signals, such as derived from a system oscillator to be continuously examined for stuck fault errors. The derived signals being examined can be half the oscillator frequency.

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In Situ Dynamic Fault Detection

      LSSD testable, "fault detection" logic circuits used in
the Holbrook and Safford programs, are described which allow high
frequency signals, such as derived from a system oscillator to be
continuously examined for stuck fault errors.  The derived signals
being examined can be half the oscillator frequency.

      The logic shown is for two signals A & B, each half the
oscillator frequency and offset by half the oscillator period, but is
extendable to any set of signals with a fixed continuous decoded
relationship.  The logic detects a signal A or B stuck in any state.
The logic and interconnection is unique because it is LSSD testable,
without relying on external clocks during fault detection operation.
Because it does not rely on external clocks for its operation, this
implementation has a two to four times frequency advantage over
previous fault detection implementations, with a reduction in
circuitry.  A capture latch "set" by the circuit's "error output"
provides detection for a single missing pulse.

      The implementation uses the following standard logic elements:
LSSD latches, inverters, "AND" gates, or "OR" gate plus a 4-way
decode.  The Decode of A & B is the set of signals t0, t1, t2
and t3, whose timing relationship is shown below.

      The stuck "fault detection" logic is comprised of a two to four
decode circuit, and four identical "stuck at" circuits whose outputs
are combined at an "OR" gate, and fed into a capture latch.  Two of
the four "stuck at" circuits and the "OR" gate are shown below.  The
decode and capture latch are not shown.  The capture latch is
optional, but is required for single missing pulse detection.

      Each "stuck at" circuit is comprised of a latch, an inverter,
and an "AND" gate.  It is the interrelationship between these
elements and the decode that provides the stuck fault detection.

      Each latch is set dominant which allows pre-conditioning prior
to, or at the beginning of, the repetitive sequence of A & B signals.
The pre-conditioning prevents false errors, and allows signals A & B
to b...