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Chip Interconnect Delay Test And Sort Technique

IP.com Disclosure Number: IPCOM000119237D
Original Publication Date: 1991-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 5 page(s) / 158K

Publishing Venue

IBM

Related People

Jaber, TK: AUTHOR

Abstract

Chip interconnect delay test is a test for the physical defects that would cause excessive delays in the path of a transition signal crossing from chip-to-chip on a multichip module (MCM) or a silicon carrier. These delays are the sum of delays on the source chip, which are normally caused by the OCD (Off-Chip Driver) circuit and any combinatorial logic that may precede it, the delay through the wire connecting the two chips and finally delay on the destination chip. The delay on the destination chip is usually caused by the receiver circuit and any combinatorial logic that may succeed it. An interconnect delay test failure is an indication that a transition signal is not making the delay paths between chips in one cycle time period.

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Chip Interconnect Delay Test And Sort Technique

      Chip interconnect delay test is a test for the physical
defects that would cause excessive delays in the path of a transition
signal crossing from chip-to-chip on a multichip module (MCM) or a
silicon carrier.  These delays are the sum of delays on the source
chip, which are normally caused by the OCD (Off-Chip Driver) circuit
and any combinatorial logic that may precede it, the delay through
the wire connecting the two chips and finally delay on the
destination chip.  The delay on the destination chip is usually
caused by the receiver circuit and any combinatorial logic that may
succeed it.  An interconnect delay test failure is an indication that
a transition signal is not making the delay paths between chips in
one cycle time period.  This test/sort technique takes advantage of
the implementation of a specially designed boundary scan string on
the chips (Fig. 1), to solve the serious problem of chip and MCM pin
inaccessibility at the second level package, and uses a Common
On-chip Processor (COP) to control the test sequencing, data transfer
and timing (Fig. 2).

      DESCRIPTION One and only one chip is designated as the driver
and all other chips are receivers.  The driver chip is the source of
zero to one and one to zero one-cycle transitions that are observed
and captured on the receiver chips.  If the transition cannot be
captured by the receiver chip in one clock cycle, then the state of
the receiver chip will be different from the expected state and the
DUT will fail the test.  It is important to note that this test is
not a complete test, that is, it will not detect every failing delay
path between chip crossings. However, it is a necessary delay test
that will cover a good number of the chip-to-chip failing delay paths
and can certainly be used for speed sorting at the MCM level.

      The transitions on the driver chip are sourced from the
boundary scan string latches which are controlled by the COP logic.
The COP also has the proper control to cycle all chips synchronously.

      SUPPORT AND CONTROL LOGIC The inverter shown in the dotted area
of Fig. 1 is needed in the boundary scan circuit to cause the
necessary transitions desired for the delay chip-to-chip wiring test.
 If a 0 to 1 transition is desired on the output pad of the driver
chip, then
1- A 0 value is scanned into the boundary scan latch (see Fig. 3)
2- A signal path is established from the output of the boundary scan
latch through MUXC, through the inverter and finally through MUXA
back into the boundary scan latch.
3- The driver chip is allowed to cycle once to launch the 0 to 1
transition.  The receiver chips are cycled twice, in sync with the
driver chip.  During the first cycle, a receiver chip captures the 0
value and on the second cycle it should capture the 1 value if no
delay faults exist.

      To control the test, a minimal change will be introduced to the
Boolean equ...