Browse Prior Art Database

Multiprocessor Initialization And Verification Method

IP.com Disclosure Number: IPCOM000119240D
Original Publication Date: 1991-Jan-01
Included in the Prior Art Database: 2005-Apr-01
Document File: 2 page(s) / 82K

Publishing Venue

IBM

Related People

Wu, RH: AUTHOR

Abstract

Disclosed is a method to initialize and verify a graphic adapter that consists of multiple processors and memory spaces. The six processors are master (M), pipe #1 (P1), pipe #2 (P2), pipe #3 (P3), pipe #4 (P4) and backend (B). Memory #1 (MEM1) is shared by host and M, and memory #2 (MEM2) is shared by M and P1. Memory #3 (MEM3) is shared by P2 and P3, and memory #4 (MEM4) is shared by P4, B and M. The primary users of MEM1, MEM2, MEM3 and MEM4 are M, P1, P3 and B, respectively. Each processor has an internal ROM code which does some processor initialization, reads a processor ID port and does a memory test if the processor is the primary user and the RUN-TEST bit is on.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Multiprocessor Initialization And Verification Method

      Disclosed is a method to initialize and verify a graphic
adapter that consists of multiple processors and memory spaces.  The
six processors are master (M), pipe #1 (P1), pipe #2 (P2), pipe #3
(P3), pipe #4 (P4) and backend (B). Memory #1 (MEM1) is shared by
host and M, and memory #2 (MEM2) is shared by M and P1.  Memory #3
(MEM3) is shared by P2 and P3, and memory #4 (MEM4) is shared by P4,
B and M. The primary users of MEM1, MEM2, MEM3 and MEM4 are M, P1,
P3 and B, respectively.  Each processor has an internal ROM code
which does some processor initialization, reads a processor ID port
and does a memory test if the processor is the primary user and the
RUN-TEST bit is on.

      The multiple processors are initialized sequentially. Host
downloads a piece of microcode (MC1) to MEM1 then resets M to invoke
M's ROM code with the RUN-TEST bit off. M's ROM code signals host at
completion of power-up then jumps to start MC1.  Running on M, MC1
controls the reset lines of the other processors to power them up
sequentially. On completion of power-up, the ROM codes of P1, P2, P3,
P4 and B signal MC1 then get into an interlock mode to read some
executable files onto their processors' internal RAM. Direct data
transfer between two processors are done through interlocked
operations.

      The multiple processors and memory are verified progressively.
(Step 1) Prior to downloading the microcode, host verifies MEM1 by
doing pattern and address tests.  Host downloads a Processor Test
Program (PTP) to MEM1 and resets M to invoke its ROM code.  At the
end, the ROM code jumps to start PTP which verifies the internal
circuitry of M and signals host for completion.  Then host downloads
a control program (MC1), some loaders (LDR1,..,LDR5) and some files
(PTP, MC2, etc.) onto MEM1, and resets M to invoke its ROM code.  M's
ROM code jumps to start MC1 which verifies the rest of the adapter
card.

      (Step 2) Running on M, MC1 does a memory test on MEM2 before
powerin...